Quote:The LVS debugger reports that my vdd and gnd pins are "unbound" pins in
my schematic. I don't know what this means
This means that your schematic pins have no equvivalent
layout pins.
Either they are really missing, means you have not drawn them.
Or Assura does not realize them for some reasons.
but then vdd and gnd are not recognized as global nets
Quote:Are vdd and gnd pins or globals in your schematic.
Are vdd and gnd pins or globals in your schematic.
If they are globals they should be called vdd! and gnd!
in the schematic and they also need a equvivalent in the
layout for LVS and extraction purpose.
Bernd