alicia8283 wrote on Jun 3rd, 2009, 7:37pm:I suppose wherever i break the loop as long as it is within the feedback loop, then i would get the same result. I get exactly the same loopgain and phase margin if i break at the 2nd and 3rd break point. But i would get different value of DC loop gain and phase margin if i break at the 1st point. :o :-/ Can anyone advise me why is the case?
Thanks in advance
Yes, you should get the same results for the same loop --- assuming you use STB or such method that takes into account currents and reverse gains.
Your original detailed diagram has two loops (thru R1 and Vout). An inner and outter loop.
You can chose to test both separately, which would change your DC gain.
I would chose to test both loops simultaneously -- I would pick the gate of the PMOS pass gate to test, which also agrees with Frank.
Good luck,
Wave