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non -idealities of PFD in verilogA (Read 13671 times)
sylak
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non -idealities of PFD in verilogA
Dec 21st, 2005, 2:38pm
 
Hi

I have a verilogA code for PFD based on a state machine. If I want to add non- ideal behaviour like narrow reset pulses into the model to mimic the actual circuit … how can it be done?

The code is similar to one the one in this website.( It is a bit too long- couldn’t post it here.)

http://www.ece.osu.edu/~wangc/DPLLVerilogA.pdf

I tried the ‘delay’ statement to delay the pulses….delay time being equal to the reset pulse width I wanted. It didn’t work. The simulator seems to totally ignore the given delay time(say 20ps or 500ps) and just take the value assigned. So the resulting waveform is like a spike rather than a pulse.

Since I wanted to have an architecture independent PFD I didn’t model it based on any logic circuits.
Would like to know if there are any particular statement or syntax I can use to get the pulses I want. Or any logic that would help!

S
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Geoffrey_Coram
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Re:  non -idealities of PFD in verilogA
Reply #1 - Dec 22nd, 2005, 9:09am
 
Did you mean "absdelay" (rather than 'delay')?  If you're using absdelay with a variable delay, did you set the optional maxdelay argument?
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sylak
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Re:  non -idealities of PFD in verilogA
Reply #2 - Dec 22nd, 2005, 9:55am
 
I tried both 'absdelay' and 'delay' .This is how I used both

x = absdelay( vlogic_low, 500p)


where x is  real  and vlogic_low is 0.

Is this right?..

S
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Andrew Beckett
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Re:  non -idealities of PFD in verilogA
Reply #3 - Dec 22nd, 2005, 1:43pm
 
Since you have a constant delay, there's no need for the maxdelay argument. That seems reasonable - although perhaps there's something wrong elsewhere in the code?

Which simulator are you using? You didn't say...

Andrew.
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Andrew Beckett
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Re:  non -idealities of PFD in verilogA
Reply #4 - Dec 22nd, 2005, 1:45pm
 
Ah, I've just seen that you mentioned in another posting that you are using hsim. So perhaps it's an implementation limitation in hsim? Check the documentation, and then contact Synopsys customer support, I guess  :)

Regards,

Andrew.
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Ken Kundert
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Re:  non -idealities of PFD in verilogA
Reply #5 - Dec 22nd, 2005, 4:59pm
 
absdelay() is a relatively expensive function to use but is able to handle arbitrary waveforms. Since you are using piecewise constant logic waveforms, you would probably be better off using transition().

-Ken
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sylak
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Re:  non -idealities of PFD in verilogA
Reply #6 - Dec 27th, 2005, 4:53pm
 
This is mainly directed at Ken but I could use anybody's suggestions.

Ken,

You had asked me to use the 'transition ' statement for producing the required pulse. I used these statements

else if (state == `same) begin
         V(up) <+ transition(vlogic_high, tdel, trise, tfall);
          V(dn) <+ transition(vlogic_high, tdel, trise, tfall);
         V(upb) <+ transition(vlogic_low, tdel, trise, tfall);
          V(dnb) <+ transition(vlogic_low, tdel, trise, tfall);
          V(up) <+ transition(vlogic_low, tdel1, trise, tfall);
         V(dn) <+ transition(vlogic_low, tdel1, trise, tfall);
         V(upb) <+ transition(vlogic_high, tdel1, trise, tfall);
         V(dnb) <+ transition(vlogic_high, tdel1, trise, tfall);
end
where tdel1= tdel+ min_pulse_width(say 20ps+50ps)
the rise and fall times are 1ps and the simualtions are run at 250Mhz input clk with trise and tfall at 20ps for both the local _osc clk and reference_clk.

My results are totally bad..even the previously obtained behavioral code doesnt seem right(initally I just had the first 4 'transisiton' statements in state 'same')

Can you tell me if this is a wrong way to get the narrow reset pulse?.

Also can you tell me what 'ttol' in 'transition' does w.r.t my code. I get spikes for the output. Is this becoz this parameter was not set?.

Has someone done this state machine based PFD with narrow reset pulses?

Thanks in advance

sylak
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Geoffrey_Coram
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Re:  non -idealities of PFD in verilogA
Reply #7 - Jan 2nd, 2006, 4:56am
 
Without giving this too much thought, I think "ttol" determines how far apart the timesteps need to be
(if the simulator requests a point within ttol of one already computed, then the previous result is used?).
So, I would try setting ttol to something on the order of 10s of ps (scale of min_pulse_width).
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Ken Kundert
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Re:  non -idealities of PFD in verilogA
Reply #8 - Jan 2nd, 2006, 2:04pm
 
You should not have the transition function inside an if statement.

Consider using something like the following
Code:
module pfd_cp (out, ref, vco);
    current out; voltage ref, vco; output out; input ref, vco;
    parameter Iout = 100u. Ileak = 0; parameter real td = 10n;
    integer state, dstate; real pulse;
    analog begin
	  @(cross(V(ref)), +1)
		if (state > –1)  state = state – 1;
	  @(cross(V(vco)), +1)
		if (state < 1)  state = state + 1;
	   pulse <+ transition(state, (state!=dstate)?td:0);
	   dstate = pulse;
	   I(out) <+ Iout*pulse + Ileak;
    end
endmodule 



I've attached a figure that shows the transfer characteristic of the PFD.

-Ken
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deadzone.gif
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sylak
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Re:  non -idealities of PFD in verilogA
Reply #9 - Jan 4th, 2006, 10:19am
 
Thank you Ken and Geoffrey!

I was able to get what I wanted !..

S
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