Vivkr,

  Fair question, but tough question. A question for
you, how are controlling simulation accuracy? If
you are just tightening reltol to get the accuracy
you need then there is probably a lot that can
be done to optimize run time.

1) Optimize the testbench to eliminate interpolation
   error, in Spectre there is an option called
   strobeperiod that can be used to force time steps
   for the FFT. You also might want to try using an
   ideal sample and hold, zvcvs.

2) Set the simulator controls appropriately for
   application.

3) Use multi-threading/table modeling to boost
   performance.

4) Try UltraSim, it is fast and correlates well with
    Spectre.

 In case you have access to SpectreRF, there was a
new option added to PSS/PAC in IC5141 USR3,
MMSIM60 USR2. The PAC equivalent of PNOISE
time domain analysis are now available.

  Time domain noise analysis allows you to measure
the noise at a point during the periodic response.
So if you chose a time point at the end of the
hold period, time domain noise analysis reports
the noise that is added to sample signal, see
the SpectreRF theory manual for more details.

 So the short answer is that PAC/PXF analysis has
been enhanced to provided funtionality equivalent to
time domain noise analysis to speed up this type
of analysis.  

                                                     Best Regards,

                                                         Sheldon

Vivkr,

  Sorry I was not clearer, the new capability for PSS/PAC
should give you the same capability for sampled distortion
analysis that PSS/PNOISE gives you for sampled noise
analysis, that is, the ability to analyze the signal and
distortion at time point during the sample/hold cycle.
So to get the complete solution, you will need run two
analysis, PSS/PNOISE for SNR and PSS/PAC for THD.
These results will provde you the SINAD. The cavaet
here is what to do about the PSS/PAC input signal. My
thinking is that I would sample a input ramp at the
maximum slew rate at the "zero-crossing" since this is
the worst case input condition for the sampling circuit.

 One other question, could you provide more information
about your simulation setup? For example,  how many
time points are in your sample and hold simulation and
what type of simulation platform you are using. The
simulation times you are quoting are times are unusually
long.  Also what machine are you using? Actually, I have
run transient Monte Carlo analysis runs on S/H circuits
and those simulations took less than a day[20 iterations].

                                                 Best Regards,

                                                    Sheldon

Hi Vivkr,

When you say your simulation has "a total of 2^14 points", do you mean you are simulating 2^14 clock cycles and taking a 2^14 point DFT?  If so, why?  I am designing a T/H that sounds very similar to yours (flipover, gain-boosted opamp, bootstrapped switches, etc) and I am able to simulate the distortion performance using only a 16 point DFT.  I don't see why you would need so many points.  I am also using much looser tolerances, but that really depends on what SFDR you want to measure (I'm designing for 80dB).

-Dan

Hi vivkr,

If you set up the simulation properly then frequency resolution is unimportant.  Let T be the clock period.  I simulate for 16*T using an input frequency of 7/(16*T), so in the DFT plot the signal is in the 7th bin and the 3rd harmonic is in the 5th bin.  If you are worried about the 3rd harmonic being too high in frequency and getting attenuated in the tracking network (not an issue for me; my tracking bandwidth is very high) then you would want to do a two-tone test.  In that case you would probablly want to use at least 32 points with inputs at 15/(32*T) and 14/(32*T) to keep the signals and intermods clustered together.

100 dB SFDR is very difficult to simulate.  I have no personal experience with this, but another student here has been working on this for a while.  One problem he ran into was using vpulse sources for clocks.  The discontinuous derivative of a vpulse source causes spectre to revert from 2nd order integration methods (trap or gear2) to first order (backward Euler, I think) near the disconinuity, which hurts accuracy.  This is a very small error that I don't notice at 80 dB SFDR, but at 100 dB SFDR it might be a problem.  You can get around this by deriving your clocks from a vsin source.  I have a VerilogA module that does this and still allows you to set the rise/fall times; let me know if you want it.  Of course you can always just sharpen-up a sinwave with inverters.  Again, this is a very small error so don't worry about it unless you've already tried everything else.

BTW, for 80 dB SFDR I am using reltol=1e-4, vabstol=1e-5, and iabstol=1e-11.  I'm not sure what you would need for 100 dB.

One more thing: any parts of your T/H that settle slowly over many clock cyles (some switched-capacitor CMFB circuits do this) will kill your SFDR if they are not completely settled.  A pss analysis will avoid this problem by guaranteeing that the solution is periodic, but it takes longer to simulate and won't work with VerilogA modules that have hidden state.  The alternative is to just let the tran simulation run long enough to settle before you measure the SFDR; for me this takes ~32 clock cycles because of my peculiar opamp topology, so I have to simulate for 48 cycles total.

Good luck!
-Dan

Hi Dan,

Thanks very much for all the inputs. I think I can save considerable time now. Also,
I think the new Cadence versions allow the user the option of choosing sinusoidal-like
transition phase for vpulse. Perhaps, this will solve the problem caused by the reversion
to backward Euler. However, I think it has not affected the accuracy of my simulations
in the past. Perhaps, it was because of the overtight tolerances in my setup.

Thanks and Best Regards
Vivek