Hello all-
I have written a two-phase clock generator in Verilog-A that generates clock waveforms with continuous derivatives.  As I understand it, a discontinuous derivative causes spectre to revert to less accurate integration methods, which can cause problems in high resolution ADC simulations.  I am using the function y(x) = tanh(x) - x*(1-tanh(3)) for the transition, which has zero derivative at x=-3 and x=3.  Unfortunately, x is a hidden state, so the cell is incompatible with spectreRF.  I have other hidden states too since I keep track of input clock edges.  Anyone have any ideas on how to eliminate the hidden state?  Is there a better way to approach the problem?  I would like to have the clock frequency defined by a sinewave input.  I tried to post the module but apparently it's too long.  Still, any help is appreciated.
-Dan

OK, lets simplify the problem.  I want a module that, when the input crosses a threshold, transitions the output.  I can think of no way to do this without capturing and storing the time at which the input crossed the threshold.

Code:

@(cross(V(in)))
    ;
V(out) <+ transition((V(in) > 0) ? +1 : -1), 0, 0);
 

Alternatively, if your model is used to drive the RF circuit, you can try using the "instrument_module" attribute, described in http://www.designers-guide.org/Forum/?board=circuit;action=display;num=112784316....

-Ken

I'm using IC5033, so I guess the instrument_module attribute  isn't an option.  What about ignore_state?

The important parameters that I want to capture in the model are:
1) nonoverlap time
2) rise time

With appropriately phase-shifted and DC-shifted (to get duty cycle < 50%) sinusoids I could place zero crossings to get the nonoverlap time correct.  But I would still need the zero crossing of these sinusoids to trigger some sort of clean transition with the proper rise time.  Again, I don't know how I can create such a transition waveform without storing the time of the zero crossing.

If the 2-phase signals should be derived from a sinewave input the best way is to model a divide by 2 circuit, which generate 2-phases with 90 degree relationship. The model have to use two integrators with positive feedback and crosscoupling controlled by the sinewave input. That is the basic model of a two latches.

I think also a nonoverlapping clock generator could be modelled with nonlinear controlled differential equations. I used the model for Simulink and VHDL-AMS to model a divide by 2 operating in the RF domain.