The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines. Dec 14th, 2017, 8:56am
  HomeHelpSearchLoginRegisterPM to admin  
 
Pages: 1
Send Topic Print
Spec&Sim driven netlist reduction (Read 6987 times)
rf-design
Senior Member
****
Offline

Reiner Franke

Posts: 160
Germany
Spec&Sim driven netlist reduction
Jun 22nd, 2005, 6:17am
 
We encounter massive performance problems with analog verfication. The circuits have about 100k-300k mixed devices and time separation of 2-5e4 (10GHz/2-5us). We could simulate schematic netlist but fail to simulate RC extracted. The memory goes above 2GB and simulation slows down more than 10x if it fits in 2GB.

From my understanding the main performance issue is that the RC extraction and simulation does not take into account that not every extracted component is gives a noticeable difference in simulation. Instead it crash the hole verification process and force the verification team to break down hierachy, both on extraction and simulation. That is errorprone and only useful for bottomup verfication of blocks.

The simulator provide from the schematic simulation enough information about speed of the voltages and the current flowing trough the device terminals. If these informations are used to specify the amount of RC or series R allowed to not impact the simulation result the reduction of the netlist or parameter selective extraction result in a verifyable netlist.

Is there any tool/flow which support the reduction or selective extraction?
Back to top
 
 
View Profile   IP Logged
August West
Community Member
***
Offline

I'll get up and fly
away

Posts: 70

Re: Spec&Sim driven netlist reduction
Reply #1 - Jun 22nd, 2005, 6:05pm
 
RF Design,
It is my understanding that UltraSim internally performs reduction on the parasitics. Also, I have recently heard that Xpedion's GoldenGate can handle massive amounts of parasitics and still run efficiently. In that case, they were simulating the parasitics associated with a package, so it is a little different from the situation you describe, but it is similar.

I personally have not used either of these tools, so I cannot vouch for them.

August
Back to top
 
 
View Profile   IP Logged
rf-design
Senior Member
****
Offline

Reiner Franke

Posts: 160
Germany
Re: Spec&Sim driven netlist reduction
Reply #2 - Jun 22nd, 2005, 11:20pm
 
August,

thank's for your information. Xpedion says that they run full extrected netlist very efficient. I could ask my colleges which run an evaluation some time ago. Ultrasim does not have the specific option for reduction (doc) and it seems to me very similar to HSIM which we where using sucessful for functional verification but not to determine performance.

There are exRC netlist reduction tools but these are digital orientied.
Back to top
 
 
View Profile   IP Logged
byang
Community Member
***
Offline



Posts: 46

Re: Spec&Sim driven netlist reduction
Reply #3 - Jul 21st, 2005, 7:28pm
 
rf-design,

What's the reason for you to use HSIM only for functional verification, but not for performance? Is it because you need to run a RF analysis such as Harmonic Balance or PSS?

For transient analysis, is there any accuracy issue with HSIM?

Thanks,

Baolin
Back to top
 
 
View Profile   IP Logged
rf-design
Senior Member
****
Offline

Reiner Franke

Posts: 160
Germany
Re: Spec&Sim driven netlist reduction
Reply #4 - Jul 25th, 2005, 2:57am
 
We actual use for analog transceiver develoment

Spectre: Most analog, performance analysis up to full chip 50-200k

SpectreRF: spot performance analsysis, mainly noise

ADS: because of tuning capabilities and TL capabilities

HSIM: full chip functional verification including digital

Smash: analog and full chip mixed

Simulink: Toplevel executeable behaviour description, with low level buildings blocks for bottom up, matches VHDL-AMS


we choose these because each operate in there own class at best.

With HSIM we have problems to set up the right tolerances for all the blocks and to get matching results to Spectre. That could possible be overcome if along to the block design accuracy specification could be incooperated into the netlist design flow. But because that is not supported by AA all work have to be done by the person who actual run the verification is missing information to make the right setup. If we set all global tolerancies to be equivalent to Spectre HSIM runs slower. If we make a sim try it take a week to get reasonable results. So we are limited by verification time.
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Trouble viewing this site? Copyright © 2002-2014 Designer's Guide Consulting. 'Designer's Guide' is a registered trademark of Designer's Guide LLC. All rights reserved.

Our colleges are not as safe as they seem. Sexual assault is pervasive and the treatment of the victim by the adminstration is often as damaging as the assault: Campus Survivors, Campus Survivors Forum.

Some of our other sites that you might find useful: Avendesora and QuantiPhy.