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How to implement the INL&DNL of ADC in verilog (Read 1946 times)
tanjp
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How to implement the INL&DNL of ADC in verilog
Dec 19th, 2004, 7:27pm
 
???,how to implement the INL&DNL of ADC in verilog-A/AMS? And why are the input resistor and the input capacitance used in the ADC?What is the function?
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sheldon
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Re: How to implement the INL&DNL of ADC in ver
Reply #1 - Dec 19th, 2004, 8:35pm
 
Hi,

  If you have access to ADE, look at the adc_8bit model,
DNL is implemented in the model. One cavaet, you may
need to add re-normailization so the output range with
DNL is correct. INL is easier, it just requires implementing a
non-linear transfer function from input to output.
For example,
 V( mid) = V( in) * gain + HD2 * V( in)^2 + HD3 * V( in)^3 ...
where V(mid) is the actual voltage that is used for the
conversion.  Depending on whether or not your ADC
model is differential out, you can drop the HD2 term.

                                                   Sheldon
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andraw
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Re: How to implement the INL&DNL of ADC in ver
Reply #2 - Jan 16th, 2005, 12:26am
 
O year, I wan to know also.
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sheldon
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Re: How to implement the INL&DNL of ADC in ver
Reply #3 - Jan 23rd, 2005, 4:52pm
 
Greetings,

  Forgot to mention, the input resistor and capacitor are
either:
1)   The input load of the ADC, driving an ADC is a very
     difficult issue.  In real ADCs, the capacitance is often
     large and non-linear.  Driving ADC are a key application
     for very high performance op-amps because of the ADC
     input load.
2)   The input resistor and capacitor maybe used to model
      the analog bandwidth of the ADC. The 3dB bandwidth
      of the input limits the maximum input frequency.

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