Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
PWM switch model	MokoKoya	3	5605	Mar 3^rd, 2006, 4:26am By: Geoffrey_Coram
Serial communication with FPGA	uzmeed	1	2164	Jan 27^th, 2006, 2:16pm By: Paul
instantiation of arrays of modules	xter	3	4620	Jan 23^rd, 2006, 4:38am By: Geoffrey_Coram
3 derivatives at 3G???	jefkat	1	1927	Jan 17^th, 2006, 6:47am By: Geoffrey_Coram
verilog-A model to check for pulse width	rudy.talukder	2	4093	Jan 13^th, 2006, 8:42am By: Ken Kundert
Modelling an oscillator using Verilog AMS	aravind406	8	113	Jan 10^th, 2006, 1:54pm By: aravind406
syntax error `include	billtsang	3	3662	Jan 10^th, 2006, 4:41am By: jbdavid
trying to check my schematic	alams	1	2308	Jan 10^th, 2006, 12:21am By: Marq Kole
Doubt in using GTKWave	bgpradeep	0	1749	Jan 4^th, 2006, 3:08pm By: bgpradeep
non -idealities of PFD in verilogA	sylak	9	13699	Jan 4^th, 2006, 10:19am By: sylak
How to pass a real value across interfaces	Sanjeev (Guest)	2	3316	Jan 2^nd, 2006, 2:10pm By: Ken Kundert
CCCS in verilog AMS not working	Saroj Rout (Guest)	1	2797	Dec 29^th, 2005, 5:24pm By: Ken Kundert
OTA verilog-AMS model	Visjnoe	2	5381	Dec 26^th, 2005, 4:17am By: Visjnoe
Phase domain model of DLL	ggr (Guest)	0	7930	Dec 23^rd, 2005, 6:03am By: ggr (Guest)
Verilog-a vs. Verilog-ams	mrbrown	2	5474	Dec 21^st, 2005, 8:01am By: Kenneth Brun Nielsen (Guest)
instantiation of modules	sylak	3	5002	Dec 21^st, 2005, 7:58am By: Geoffrey_Coram
Verilog counter (newbie)	athlon	0	1704	Dec 20^th, 2005, 9:07pm By: athlon
question on varactor model	vishnu (Guest)	1	2105	Dec 16^th, 2005, 2:02pm By: vishnu (Guest)
Verilog-A RAM Model	Zorro	3	8345	Dec 1^st, 2005, 4:50am By: Zorro
Read from a file	Zorro	4	4297	Dec 1^st, 2005, 4:39am By: Zorro

Pages: 1 ... 47 48 49 50 51 ... 56

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