Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
SAR ADC SNDR degradation due to bins around DC « Pages 1 2 »	niloun	24	6031	Apr 23^rd, 2018, 4:05am By: niloun
DNL/INL calculation using histogram testing of sinusoidal input	niloun	2	92	Apr 5^th, 2018, 9:25am By: niloun
how to consider reference voltage's noise impact on adc output?	vincentleung	2	2201	Apr 4^th, 2018, 11:33pm By: Jacki
Moved: mixed signal simulation of a transmitter running very slow - Started by: nischaybm This Topic has been moved to Circuit Simulators by Ken Kundert
Why is the SNDR of signal-delta ADC is not dominated by mismatch?	Jacki	3	111	Mar 20^th, 2018, 1:44am By: Jacki
Why do we need CDS, not only use auto-zero instead?	Jacki	1	1832	Mar 11^th, 2018, 5:26am By: Jacki
Load limit on the TIEHI and TIELO cells	pkd	0	55	Feb 6^th, 2018, 7:36pm By: pkd
Why did the post-layout simulation result incorrectly	nxthuan512	1	1695	Jan 27^th, 2018, 8:45am By: Andrew Beckett
Moved: Fully Differential Opamp Simulation with Switched Capacitor CMFB - Started by: repah This Topic has been moved to Circuit Simulators by Ken Kundert
Moved: SNR of Fully Different Opamp with SC CMFB using Spectre and MATLAB - Started by: repah This Topic has been moved to Circuit Simulators by Ken Kundert
How to find out the BW of a dynamic latch, such as strong arm latch?	Frank_Heart	2	87	Nov 28^th, 2017, 4:30am By: Berti-2
SAR ADC KT/C Noise	Mikay	8	11295	Nov 17^th, 2017, 10:27am By: Frank_Heart
Passive adder in continuous time delta sigma modulator	polyam	7	2145	Nov 16^th, 2017, 10:16pm By: Frank_Heart
SAR ADC SNR variations for different FFT numbers « Pages 1 2 3 »	niloun	31	16886	Nov 16^th, 2017, 3:23pm By: Frank_Heart
Problem with Ideal current steering DAC in a CT DSM	polyam	10	6595	Nov 16^th, 2017, 2:55pm By: Frank_Heart
design consideration for a low noise dynamic comparator with preamp.	yvkrishna	12	8081	Nov 16^th, 2017, 2:47pm By: Frank_Heart
Moved: Sigma Delta Modulator SNDR with Monte-Carlo Simulation in Cadence - Started by: MehdiOranji This Topic has been moved to Circuit Simulators by Ken Kundert
SRAM design for external EEPROM	kocchop	0	47	Oct 20^th, 2017, 1:30pm By: kocchop
Waveforms through Class E amplifier	atifnawaz08	0	40	Oct 11^th, 2017, 8:39am By: atifnawaz08
Moved: Port declaration in ADC model - Started by: samiran This Topic has been moved to Verilog-AMS by Ken Kundert

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