Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
VerilogA CDR model: RMS jitter and BER	djr77	2	10066	Apr 28^th, 2006, 1:28pm By: djr77
Negative setup time and postive hold time?	sylak	2	11458	Apr 18^th, 2006, 1:34am By: aamar
PCI-Express jitter frequency definition	neoflash	10	2190	Dec 22^nd, 2005, 5:03am By: neoflash
Differential Interface	Linus (Guest)	2	4356	Nov 15^th, 2005, 11:19pm By: Linus (Guest)
Request paper/doc on digital CDR loop analysis	neoflash	3	6630	Nov 3^rd, 2005, 1:22pm By: Paul
LVDS RX	yagi	0	3497	Oct 15^th, 2005, 6:04pm By: yagi
Why we need Viterbi Decoder in High speed link?	raymond_luo2003	3	5230	Oct 14^th, 2005, 6:30am By: raghunath cherukuri (Guest)
PCI	stevy_y	2	4337	Sep 25^th, 2005, 2:37pm By: Paul
question on lvds	navin_kumar	4	6053	Sep 8^th, 2005, 12:20am By: navin_kumar
deterministic jitter in serdes receive data	feiyue	3	921	Mar 31^st, 2005, 8:19pm By: feiyue
deadzone in PLLs	cAddIE	2	5671	Jan 31^st, 2005, 11:17pm By: Frank Wiedmann
eye diagrams in cadence	tony (Guest)	2	7938	Nov 2^nd, 2004, 4:56pm By: jbdavid
pecl cap loading reflection	raymyl	0	3271	Feb 15^th, 2004, 5:29pm By: raymyl
I/O Pads	seagull	1	618	Oct 30^th, 2003, 12:59pm By: circuit_master_RT

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