Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
plot node waveform from assura ext layout	CDR	2	3728	Jul 6^th, 2005, 4:30pm By: CDR
Is Assura good enough for 0.13um CMOS verification	raymond_luo2003	4	6283	Jun 19^th, 2005, 1:53pm By: Paul
why Assura DRC hangs	asdf	1	3051	Jun 15^th, 2005, 10:54pm By: Andrew Beckett
The extraction problem of BJT transistor	Question	7	10590	Jun 15^th, 2005, 3:01am By: Robert
Diva extract can't extract symbol pin	CDR	3	91	Jun 9^th, 2005, 11:31pm By: Robert
Assura Problem	Tom	1	2871	May 20^th, 2005, 12:25pm By: DReynolds
Assura RCX extract problem	lanneko	1	2811	Apr 25^th, 2005, 11:35am By: lanneko
Specify Terminals of a 3-terminal Inductor	Ray_Lin	2	4126	Apr 7^th, 2005, 1:54am By: Ray_Lin
Assura can't be loaded due to shared object file	CDR	3	7563	Mar 20^th, 2005, 11:19pm By: Andrew Beckett
Assura lvs problem under linux	stephen	5	1270	Feb 15^th, 2005, 11:39pm By: Paul
Problem in installing Assura in ace446	rpaul	2	4446	Nov 8^th, 2004, 10:59am By: rpaul
Can Layout Extraction be made nonblocking?	stephen	3	4934	Jul 27^th, 2004, 9:56pm By: Andrew Beckett
Cadence bug with via/contact resistance extraction	stephen	3	5649	Jul 27^th, 2004, 2:56pm By: Andrew Beckett
The problem in PDRACULA	Aigneryu	5	113	May 23^rd, 2004, 4:29am By: staric
Problem with divaDRC.rul -- TSMC0.25um	harry_ece	2	5639	Feb 9^th, 2004, 5:30am By: okguy

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