Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
what wrong with the CadenceIC?	wjx197733	3	6911	Feb 13^th, 2006, 1:58am By: bernd
Questions on Cadence tool, icfb	shchangtx	2	3770	Feb 8^th, 2006, 6:48am By: shchangtx
how to get the right resistor device layer in LVS	jaylin79	3	3967	Feb 7^th, 2006, 9:35pm By: jaylin79
What does this warning mean in dracula?	jaylin79	1	2494	Feb 7^th, 2006, 10:48am By: Andrew Beckett
Team Design Manager	asdf	5	6020	Feb 5^th, 2006, 8:46am By: Andrew Beckett
What tool do you use to make graphics for docs?	Croaker	2	918	Feb 2^nd, 2006, 7:14am By: Croaker
ASSURA and pins	paguirre	2	4472	Jan 24^th, 2006, 2:32pm By: paguirre
How to add L and W of resistor in CDL netlist	jaylin79	3	6249	Jan 19^th, 2006, 1:26am By: bernd
How to solve this LVS error?	jaylin79	5	6615	Jan 17^th, 2006, 9:54pm By: jaylin79
what is the most necessory definition in a techfil	jaylin79	2	3961	Jan 12^th, 2006, 5:23pm By: jaylin79
Can .sf file be imported into virtuoso layout edit	jaylin79	7	11667	Dec 25^th, 2005, 7:34pm By: jaylin79
Parasitic extraction with Assura	asdf	7	2031	Nov 4^th, 2005, 5:15am By: Andrew Beckett
Plotting from Virtuoso	Godfrey	6	11347	Oct 31^st, 2005, 5:18am By: jmurdoch (Guest)
Assura LVS passes incorrect	asdf	1	3128	Oct 12^th, 2005, 1:41pm By: Andrew Beckett
Re: Printing Schematic	Andrew Beckett	0	2549	Aug 14^th, 2005, 12:15am By: Andrew Beckett
sub schematic can not be edited	jay_lin	8	1914	Aug 4^th, 2005, 2:49am By: Andrew Beckett
How to export a flatten netlist in icfb	xuel	1	3207	Jul 31^st, 2005, 9:43pm By: Andrew Beckett
Schem Entry: Wires disappear during copying	SumaGazi	0	2468	Jul 7^th, 2005, 3:37am By: SumaGazi
Virtuoso Schematic UserDefined Annotation	rf-design	0	2537	Jun 22^nd, 2005, 5:57am By: rf-design
Wire Color in Schematics	uncle_ezra	3	78	Jun 21^st, 2005, 8:29pm By: Andrew Beckett

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