Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Middlebrook's General Feedback Theorem	blue111	1	838	Jul 27^th, 2020, 11:45am By: Frank Wiedmann
Amplifier 2nd second stage topology clarification	Chetan Kulkarni	2	1133	Jul 7^th, 2020, 4:33am By: Chetan Kulkarni
Trade-off between LDO max Iout AND PSRR « Pages 1 2 3 »	blue111	37	6469	Jul 2^nd, 2020, 5:17am By: blue111
What and why is 2N3904 BJT transistor?	neoflash	3	946	Jun 7^th, 2020, 1:00am By: Andrew Beckett
Analog CMOS IC layout: DRC, DFM, DFR.	Tako	2	998	Jun 5^th, 2020, 3:19am By: Tako
Moved: Increasing the standard deviation of models in cadence - Started by: dnw This Topic has been moved to Circuit Simulators by Ken Kundert
comparator offset voltage simulation veriloga model	Hesham	8	235	May 13^th, 2020, 7:33am By: Felddo
Ring Oscillator Pre vs. Post Layout Frequency Shift	melvin1109	3	1464	Apr 3^rd, 2020, 5:36pm By: Horror Vacui
Split Array Capacitive DAC	Bean Nakamura	4	1207	Mar 17^th, 2020, 8:12pm By: Bean Nakamura
Switching power in cap	dnw	3	1018	Mar 12^th, 2020, 4:51am By: rajasekhar
pnoise/jitter and pnoise/time average discrepancy with Cadence Spectre	threepwood	0	584	Feb 13^th, 2020, 10:39am By: threepwood
VCO	MILIND BHANDARI	2	1278	Jan 12^th, 2020, 11:55pm By: subtr
DAC noise analysis?	Jacki	2	1109	Jan 6^th, 2020, 9:08am By: neoflash
Scaling of Sampling clock in CT-SDM ADC	neoflash	0	574	Jan 2^nd, 2020, 4:23pm By: neoflash
Moved: STB vs AC analysis - different result - Started by: Andrew94 This Topic has been moved to Circuit Simulators by Ken Kundert
How to speed up RJ sim for DLL including Regulator	aks	4	1264	Dec 9^th, 2019, 2:18am By: aks
Noise sims for switched capacitor amplifiers	vm511	0	616	Nov 25^th, 2019, 12:10pm By: vm511
anti-aliasing filter for ADCs	polyam	1	918	Oct 4^th, 2019, 7:28am By: Andrew Beckett
Poles and zeros in all pass filter.	Jacki	5	1278	Sep 9^th, 2019, 5:47am By: Jacki
MOSFET OP parameters for a small-signal model	IBurmistrov	1	831	Sep 8^th, 2019, 10:48pm By: IBurmistrov

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