Forum Forum Verilog-AMS Analysis Modeling Design Theory Books Welcome, Guest. Please Login or Register. Please follow the Forum guidelines. Sep 24th, 2017, 8:51am     HomeHelpSearchLoginRegisterPM to admin     The Designer's Guide Community Forum › Design › Analog Design Pages: 1 2 3 ... 131   Subject Started by Replies Views Last post How to design a PLL with a cycle to cycle jitter under 300ps? how to simulate? hezea 2 66 Yesterday at 9:37pm By: hezea Chopping inside or outside the feedback loop? jdp 0 18 Sep 22nd, 2017, 11:14pm By: jdp Deriving Gm of circuit blue111 8 1413 Sep 22nd, 2017, 3:33pm By: sheldon Question about MOSFET model options in a commercial process. tenso 0 91 Sep 2nd, 2017, 5:26pm By: tenso Differential pair with active current mirror and realistic current source blue111 0 121 Sep 2nd, 2017, 12:22am By: blue111 Gain of BiCMOS gm-cell blue111 2 122 Sep 2nd, 2017, 12:15am By: blue111 Delay circuit for analog signal naina 3 221 Aug 21st, 2017, 4:51pm By: lukeS Finger or multiplier in MOS transistors polyam 3 164 Aug 21st, 2017, 4:44pm By: lukeS 2nd order SDM followed by sinc2 decimation filter? neoflash 7 329 Aug 17th, 2017, 4:19pm By: neoflash Correct biasing scheme for Common Drain stage exp 4 462 Aug 10th, 2017, 3:50am By: Berti-2 Reducing resistors in a loop filter of a type II PLL to hasten locking Hercules Poirot 0 83 Aug 8th, 2017, 8:51am By: Hercules Poirot Why should CP - PLL have limited bandwidth? subtr 4 617 Aug 8th, 2017, 5:43am By: Hercules Poirot settling time of charge pump in a CPPLL. Jacki 8 372 Aug 8th, 2017, 5:15am By: Hercules Poirot First Top-plate sampling SAR ADC DanielLam 0 104 Aug 4th, 2017, 1:31pm By: DanielLam Moved: Ideal SH time interleaving - Started by: John Rankin This Topic has been moved to Verilog-AMS by Ken Kundert Question on mutual capacitance change on other neighboring conductors neoflash 1 141 Jul 31st, 2017, 9:36am By: Maks PVT of nulling resistor in miller compensation. Jacki 7 362 Jul 28th, 2017, 12:56pm By: Jacki SAR ADC C-DAC noise analysis neoflash 2 185 Jul 26th, 2017, 6:16pm By: neoflash Problems when increasing the frequency in ring oscillator Abdallah Kamal 1 182 Jul 18th, 2017, 1:25am By: Jacki Switched-capacitor Bandgap Reference-Switch Sizing prietess 4 375 Jul 10th, 2017, 9:55am By: prietess Pages: 1 2 3 ... 131 Normal Topic Sticky Topic Locked Topic Sticky Locked Topic Moved Topic Global Announcement Hot Topic (More than 10 Replies) Very Hot Topic (More than 25 Replies) You can view Topics in this Board. You cannot post replies to Topics in this Board. You cannot start new Topics in this Board. You cannot start Polls in this Board. Forum Jump » » 10 most recent Posts » 10 most recent Topics Design  - RF Design »» Analog Design   - Mixed-Signal Design   - High-Speed I/O Design   - High-Power Design   - Mixed-Technology Design Analog Verification  - Analog Functional Verification   - Analog Performance Verification Measurements  - RF Measurements   - Phase Noise and Jitter Measurements   - Other Measurements Modeling  - Semiconductor Devices   - Passive Devices   - Behavioral Models   - Transmission Lines and Other Distributed Devices Design Languages  - Verilog-AMS   - VHDL-AMS Simulators  - Circuit Simulators   - RF Simulators   - AMS Simulators   - Timing Simulators   - System Simulators   - Logic Simulators Other CAD Tools  - Entry Tools   - Physical Verification, Extraction and Analysis   - Unmet Needs in Analog CAD General  - Tech Talk   - News   - Comments and Suggestions   - Opportunities   ‹ Home The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. Opportunities What's New Links Experts Perspective Submissions Calculator Trouble viewing this site? Copyright © 2002-2014 Designer's Guide Consulting. 'Designer's Guide' is a registered trademark of Designer's Guide LLC. All rights reserved. Community Web Advertise on this site.

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