Forum Forum Verilog-AMS Analysis Modeling Design Theory Books Welcome, Guest. Please Login or Register. Please follow the Forum guidelines. Oct 19th, 2018, 11:47pm     HomeHelpSearchLoginRegisterPM to admin     The Designer's Guide Community Forum › Design › Analog Design Pages: 1 2 3 ... 135   Subject Started by Replies Views Last post How to understand "kTC" noise? A Kumar R 0 23 Yesterday at 6:06am By: A Kumar R General method for phase-locked loop filter analysis and design blue111 0 171 Oct 16th, 2018, 9:09pm By: blue111 PMOS current source I-V characteristics Harian 4 848 Oct 15th, 2018, 11:23am By: Nyquist effects of dummy metal fill parasitic capacitor on stability/Analog Design analog_design 0 38 Oct 14th, 2018, 6:09am By: analog_design what are these two circuits? alan kim 1 77 Oct 11th, 2018, 1:26pm By: alan kim Moved: I have a question - Started by: nguyen This Topic has been moved to RF Simulators by Ken Kundert Tow stage Op-Amp common mode feedback Majid 7 680 Sep 29th, 2018, 2:09pm By: vroy_92 Settling in a Pipelined ADC rabeh4 3 1338 Sep 23rd, 2018, 9:23am By: Mos non-overlapping clock issue in a SC delta sigma modulator polyam 4 163 Sep 8th, 2018, 5:30pm By: polyam Moved: ADE-L spectre simulation can't stop - Started by: xiaoli This Topic has been moved to Circuit Simulators by Ken Kundert Pseudo-Differential OTA Gm vs Vin plot styxies 0 115 Aug 30th, 2018, 4:25pm By: styxies Rise and fall time of inverter pashtp 1 136 Aug 27th, 2018, 3:34pm By: DanielLam Maximum metal length and single connection routing in Layout XL frasheed 0 95 Aug 25th, 2018, 4:38pm By: frasheed Post-layout simulation of sigma-delta modulators "error" PCCDA 0 96 Aug 23rd, 2018, 2:08pm By: PCCDA Poll: Charge Sharing SAR ADC Rajesh210691 0 133 Aug 22nd, 2018, 9:22am By: Rajesh210691 combined Bipolar-MOSFET current mirror bki 1 158 Aug 20th, 2018, 8:42am By: Horror Vacui VDSAT more than VGS-VTh cmosa 6 912 Aug 6th, 2018, 11:48am By: Nyquist How to achieve a high SNDR single-ended delta-sigma modulator? Jacki 2 330 Jun 28th, 2018, 9:50am By: Jacki Moved: Why every company asks for experience to work in Analog IC design - Started by: VK This Topic has been moved to Opportunities by Ken Kundert Moved: How to calculate phase noise of PLL in cadence? - Started by: pashtp This Topic has been moved to RF Simulators by Ken Kundert Pages: 1 2 3 ... 135 Normal Topic Sticky Topic Locked Topic Sticky Locked Topic Moved Topic Global Announcement Hot Topic (More than 10 Replies) Very Hot Topic (More than 25 Replies) You can view Topics in this Board. You cannot post replies to Topics in this Board. You cannot start new Topics in this Board. You cannot start Polls in this Board. Forum Jump » » 10 most recent Posts » 10 most recent Topics Design  - RF Design »» Analog Design   - Mixed-Signal Design   - High-Speed I/O Design   - High-Power Design   - Mixed-Technology Design Analog Verification  - Analog Functional Verification   - Analog Performance Verification Measurements  - RF Measurements   - Phase Noise and Jitter Measurements   - Other Measurements Modeling  - Semiconductor Devices   - Passive Devices   - Behavioral Models   - Transmission Lines and Other Distributed Devices Design Languages  - Verilog-AMS   - VHDL-AMS Simulators  - Circuit Simulators   - RF Simulators   - AMS Simulators   - Timing Simulators   - System Simulators   - Logic Simulators Other CAD Tools  - Entry Tools   - Physical Verification, Extraction and Analysis   - Unmet Needs in Analog CAD General  - Tech Talk   - News   - Comments and Suggestions   - Opportunities   ‹ Home The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. Opportunities What's New Links Experts Perspective Submissions Calculator Trouble viewing this site? Copyright © 2002-2018 Designer's Guide Consulting. 'Designer's Guide' is a registered trademark of Designer's Guide LLC. All rights reserved. Community Web Advertise on this site.

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