Forum Forum Verilog-AMS Analysis Modeling Design Theory Books Welcome, Guest. Please Login or Register. Please follow the Forum guidelines. Feb 18th, 2019, 12:25am     HomeHelpSearchLoginRegisterPM to admin     The Designer's Guide Community Forum › Design › Analog Design Pages: 1 2 3 ... 136   Subject Started by Replies Views Last post Moved: RC oscillator cannot oscillate - Started by: Jacki This Topic has been moved to Circuit Simulators by Ken Kundert why using an inverter with hysteresis bki 1 183 Jan 21st, 2019, 9:15am By: James_T SNDR calculation in a delta sigma DAC polyam 2 232 Jan 13th, 2019, 4:51am By: jdp Output swing, threshold voltage and body effect tenso 0 104 Jan 8th, 2019, 10:04am By: tenso Moved: common gate configuration - Started by: srinivasan0901 This Topic has been moved to Circuit Simulators by Ken Kundert Moved: Some questions about SpectreRF and sampled circuits - Started by: ZY He This Topic has been moved to RF Simulators by Ken Kundert Paper showing evolution of intrinsic gain vs. min. channel length? spectrallypure 2 212 Dec 29th, 2018, 4:15pm By: vroy_92 Delta Sigma digital to analog converter (DAC) polyam 1 213 Dec 13th, 2018, 4:41pm By: polyam MDAC for Pipeline ADC - Timing Analysis - Part 2 repah 2 349 Dec 8th, 2018, 4:28pm By: polyam regarding W/L ratio of transistor srinivasan0901 4 361 Dec 1st, 2018, 7:51am By: polyam MDAC for Pipeline ADC - Timing Analysis repah 1 200 Nov 29th, 2018, 12:50pm By: DanielLam Single Ended Switched Capacitor Opamp to Differential Conversion repah 1 169 Nov 28th, 2018, 4:55pm By: repah Bridge Rectifier niloun 1 311 Nov 21st, 2018, 7:31pm By: sisc1525 IC Architecture engrkei 4 512 Nov 21st, 2018, 7:28pm By: sisc1525 Any idea for a all-PMOS current reference. Jacki 0 203 Nov 16th, 2018, 5:59am By: Jacki Application for Type-I of PLLs Peelin 1 234 Nov 15th, 2018, 12:28am By: vroy_92 Telescopic Opamp Design Using Gm/ID Methodology repah 0 182 Nov 13th, 2018, 5:17pm By: repah Clocking and Timing of SC Sigma Delta Modulator repah 5 371 Nov 13th, 2018, 4:57pm By: repah DAC input full-scale range in #of bit polyam 0 157 Nov 12th, 2018, 6:39pm By: polyam How to understand "kTC" noise? A Kumar R 1 337 Oct 28th, 2018, 5:16pm By: Maks Pages: 1 2 3 ... 136 Normal Topic Sticky Topic Locked Topic Sticky Locked Topic Moved Topic Global Announcement Hot Topic (More than 10 Replies) Very Hot Topic (More than 25 Replies) You can view Topics in this Board. You cannot post replies to Topics in this Board. You cannot start new Topics in this Board. You cannot start Polls in this Board. Forum Jump » » 10 most recent Posts » 10 most recent Topics Design  - RF Design »» Analog Design   - Mixed-Signal Design   - High-Speed I/O Design   - High-Power Design   - Mixed-Technology Design Analog Verification  - Analog Functional Verification   - Analog Performance Verification Measurements  - RF Measurements   - Phase Noise and Jitter Measurements   - Other Measurements Modeling  - Semiconductor Devices   - Passive Devices   - Behavioral Models   - Transmission Lines and Other Distributed Devices Design Languages  - Verilog-AMS   - VHDL-AMS Simulators  - Circuit Simulators   - RF Simulators   - AMS Simulators   - Timing Simulators   - System Simulators   - Logic Simulators Other CAD Tools  - Entry Tools   - Physical Verification, Extraction and Analysis   - Unmet Needs in Analog CAD General  - Tech Talk   - News   - Comments and Suggestions   - Opportunities   ‹ Home The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. Opportunities What's New Links Experts Perspective Submissions Calculator Trouble viewing this site? Copyright © 2002-2018 Designer's Guide Consulting. 'Designer's Guide' is a registered trademark of Designer's Guide LLC. All rights reserved. Community Web Advertise on this site.

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