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1  Design / Analog Design / Re: Settling Time Simulation of a Differential Opamp
 on: Today at 7:57pm 
Started by repah | Post by repah
Hello,

Thank you.

I guess what I am asking is in the figure I attached - the two "vcmi" inputs are the same - to the step and also to the opamp.  Is this correct ?  This will be the input common mode of the signal and must be within the input common mode range of the opamp.

Next, yes, I am also doing a Differential TIA.  Can you provide guidance, papers or any resources on how to design the input common mode feedback to fix VCM of a differential TIA ?

Also what do you mean by fully titled cases at the output ?  My common mode output voltage is 0.9V.  That also has to be in the output common mode range of the output of the opamp.  Is this correct ?  What do you mean again, by fully tilted cases ?

Thank you again.

2  Design / Analog Design / Re: DC characteristics  of Rail to Rail buffer (65nm)
 on: Yesterday at 11:09pm 
Started by kabir_fakir | Post by Frank_Heart
Hi, kabir,

 There is always gain drop when Vout approaches to rail, completely driving PMOS (or NMOS) side to triode region, such that the systematic offset gains up, if your feedback loop still holds and nothing is broken (working in triode region) in previous gain stages.  

 Say you have 3-stage amplifier, the 1st & 2nd stage gain is already high enough to bring systematic offset below 1mV. But remember you are going to have mis-match in real circuit, which could drive the 1st & 2nd stage broken in this case. So your overall offset will be much larger. This might be the reason, you get much higher offset than your schematic results.  You should run some MC to check the offset @ fully titled cases.

Regards,
Frank

3  Design / Analog Design / Re: architecture trade off on input loading of sigma-delta ADC
 on: Yesterday at 10:57pm 
Started by neoflash | Post by Frank_Heart
Hi, Neo,

 I think it should be similar. We always want the pre-amp gain to be as large as possible to degrade ADC noise, referring to input. Of course, the degraded linearity should be within spec, if it is for wide band applications.

Regards,
Frank

4  Design / Analog Design / Re: Intuitively find poles and zeros in a RC circuit
 on: Yesterday at 10:53pm 
Started by curious | Post by Frank_Heart
also check Elmore delay which might be useful to you.  -Frank

5  Design / Analog Design / Re: Settling Time Simulation of a Differential Opamp
 on: Yesterday at 10:50pm 
Started by repah | Post by Frank_Heart
Hi, Repah,

  If you want to do a CM step transient, then just short inputs and apply, 400mV <-> 500mV on the input.  

 If you want to do a differential step transient (say 200mV step), apply Vip = 400mV (CM) --> 500mV and Vin = 400mV (CM) --> 300mV.

 Regarding to how to set input/output VCM.  Usually input VCM is decided by its previous stage. You got the spec from system, and design your amplifier basing on this.  (There are also applications you need to design input common mode feedback circuit to fix your VCM, if it is used in a differential TIA. )

 Output VCM is set by your output CMFB circuit. The value is usually decided what your amplifier is going to drive, and of course you have to make sure output stage is happy working at fully tilted cases.

-Frank

6  Simulators / Circuit Simulators / DFT Assistance
 on: Yesterday at 6:22pm 
Started by MWJ1975 | Post by MWJ1975
Hi,

I am trying to simulate the DFT response in Cadence. I have constructed an LC Cross-Coupled oscillator operating at approximately 1GHz. I used the 'frequency' function in the calculator to obtain the value above and I am getting a free running frequency of 1.005GHz. I would like to analyze the harmonics of the signal (at least of to the 4th harmonic).

I attempted to use the DFT function but I am getting an error when I try to plot my response. The first thing I did was run a transient analysis for 300ns. I then clipped the waveform from 50ns to 100ns. Setting the 'From' and 'To' of the DFT function is where my main confusion arises.

From the initial values set, I am assuming this is the start and stop time. I would like to examine 1GHz and 4GHz, so my logic was to start at 0.2n to 2n. Which I was assuming would include frequencies from 500MHz to 5GHz. I chose a sample value of 2^15 and left all the other options to the default value. I am not able to get any sort of response.

I am having trouble locating the documentation for the DFT function, so I last resorted to this. Could anyone provide any tips or relevant information? Thank you.

7  Measurements / RF Measurements / DFT verification
 on: Yesterday at 3:03pm 
Started by MWJ1975 | Post by MWJ1975
Hi,

I am trying to simulate the DFT response in Cadence. I have constructed an LC Cross-Coupled oscillator operating at 1GHz. I used the 'frequency' function in the calculator to obtain the value above. I would like to analyze the harmonics of the signal (at least of to 4GHz).

I attempted to use the DFT function but I am getting an error when I try to plot my response. The first thing I did was run a transient analysis for 300ns. I then clipped the waveform from 50ns to 100ns. Setting the 'From' and 'To' of the DFT function is where my main confusion arises.

From the initial values set, I am assuming this is the start and stop time. I would like to examine 1GHz and 4GHz, so my logic was to start at 0.2n to 2n. Which I was assuming would include frequencies from 500MHz to 5GHz. I chose a sample value of 2^15 and left all the other options to the default value. I am not able to get any sort of response.

I am having trouble locating the documentation for the DFT function, so I last resorted to this. Could anyone provide any tips or relevant information? Thank you.

8  Design / Analog Design / Re: Settling Time Simulation of a Differential Opamp
 on: Yesterday at 12:14pm 
Started by repah | Post by repah
Hello,

Thank you for your response.

The input signals of this test bench is just the step that I am applying to the opamp and the input common mode voltages.

Should I be imputing a sine wave on top of the common mode voltages for this test bench (for settling time) instead of just a step and the common mode voltage ?  I am confused on how to set this test bench up.

I have questions regarding input common mode voltages of differential opamps and associate test bench for measuring settling time in transient.

I want to design a PMOS input folded cascode fully differential opamp.  I would like the input common mode voltage to be 400mV and the output common mode voltage to be 900mV (say 0.18um CMOS technology).  

My questions are :

1) how does one design for an input common mode voltage of 400mV on the differential opamp ?  Is this basically the voltage of the combination of the Vov of the diff pair current source and the vgs of the diff pair transistor ?  Sizing and biasing them properly to achieve the 400mV input common mode voltage ?

2) how does one design for output common mode voltage of the differential opamp ?  Is this sizing the output cascode stage of the folded cascode differential opamp to achieve a swing around this common mode voltage ?

3) When I size and bias my opamp to achieve this input common mode voltage - then using the test bench I have shown the input common mode voltage is set to this value, in my case 400mv?

Thank you.

9  Design / Mixed-Technology Design / Sub 1ohm mems muxing switch
 on: Yesterday at 10:57am 
Started by neoflash | Post by neoflash
Guys,

Is there mems device that can do analog signal muxing? Provide low Ron and small form fact size?

Thanks,
Neo

10  Design / Analog Design / Re: Fully Differential Amplifier and output common-mode voltage
 on: Yesterday at 10:54am 
Started by Anna901 | Post by Frank_Heart
the ouput is clipped with Vin=500mV. -Frank

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