1 
Simulators / Circuit Simulators / Re: Simulation for Ferroelectric Varactor
on: Today at 12:05pm 
Started by aguntuk  Post by Ken Kundert 
If the drive voltage is 1, then plotting the current is the same as plotting admittance (not impedance). And if the admittance is purely imaginary and the frequency is 1/2π, then plotting the admittance is the same as plotting the capacitance in Farads.
How are you passing an amp through your capacitor. Is C_{0} on the order of a Farad?
Ken 

2 
Simulators / Circuit Simulators / Re: Simulation for Ferroelectric Varactor
on: Today at 7:42am 
Started by aguntuk  Post by aguntuk 
V=I*Z=I/(jwc) , so C=I/(w*V) if V=1,w=1 then C=I. w=2×Π×f, if I wanna have w=1 I have to setup f=0.159 Hz
Now I put this frequency in the analysis... but the current which gives me actually the impedance is not the capacitance that should be for a varactor. My verilogA model contains leakage current also which also counts. This curve is ok for the current curve but with the frequency and ac magnitude of 1V the conversion to capacitance is opposite.


4 
Simulators / Circuit Simulators / Re: Simulation for Ferroelectric Varactor
on: Today at 2:22am 
Started by aguntuk  Post by aguntuk 
Ken Kundert wrote on Dec 2^{nd}, 2018, 5:07am: Run an AC analysis.
 Configure the AC analysis so that it sweeps DC voltage rather than frequency.
 Plot the current through the capacitor.
You are left with two free variables: AC magnitude of the source and the analysis frequency. Set one to 1, set the other so that the output current is scaled so that you are plotting in Farads directly. Ken thanks for your answer. I like this manual idea. I am confused about the analysis frequency. I put the ac magnitude to 1 Now in ac analysis, what should be the analysis frequency so that I can make it to farad? I didn't get the conversion here. Can you help me with this? 

6 
Design / Analog Design / Delta Sigma digital to analog converter (DAC)
on: Yesterday at 4:40pm 
Started by polyam  Post by polyam 
Hi,
I am designing a 16bit deltasigma DAC to cover 3MHz bandwidth. It consists of the interpolation filter, deltasigma modulator, DAC and reconstruction filter. Reconstruction filter generally consists of a switched capacitor filter followed by a buffer and a continuous time filter. The interpolation factor is 128 and I am clocking the deltasigma modulator at 800MHz. I haven't seen any deltasigma DAC paper at this sampling rate with such a structure. Anyways, 1 Is it really feasible to have a deltasigma DAC at this sampling rate? Assuming that the deltasigma modulator operates at this rate (it is a placed and routed digital circuit), the main bottleneck is the switched capacitor filter. If it is feasible, what is the rule of thumps for the unity gain bandwidth of the OTA used in the switched capacitor filter?
I am adding the block diagram of the DAC.
Thanks


7 
Simulators / RF Simulators / HFSS eigenmode
on: Yesterday at 12:40am 
Started by farshad  Post by farshad 
Dear all, I simulate a ring oscillator with HFSS eigenmode and get resonance frequency around 7.8 GHZ. to check the simulation, in driven modal I used same resonator coupled to a transmission line. the dip in the S21 is not at 7.5 GHz but it's at 8 GHz, any body can explain the difference? Best, Farshad 

8 
Design / Analog Design / Re: MDAC for Pipeline ADC  Timing Analysis  Part 2
on: Dec 8^{th}, 2018, 4:28pm 
Started by repah  Post by polyam 
VDD and GND are the supply and ground of the switches. If it is a simple transmission gate it means that the bulks are connected to VDD and GND for PMOS and NMOS respectively. The MDAC essentially works with two nonoverlapping clocks and their delayed version. P1 and P2 are the nonoverlapping clocks. P1D is the delayed version of P1. P2D is the delayed version of P2.
Hope it's a good guess!


9 
Modeling / Behavioral Models / Re: VerilogA : Behavioral model analyzer/optimizer
on: Dec 7^{th}, 2018, 4:28am 
Started by AS  Post by Andrew Beckett 
Spectre has an "AHDL Linter". This can be turned on in ADE via Simulation>Options>Analog and is on the Miscellaneous tab. From the command line it's the ahdllint option.
There are some static checks which will then appear in the normal simulator output log, and then some checks during simulation for potential performance issues or improvements (in ADE the Linter log can be shown from the Simulation menu).
Regards,
Andrew. 

