The Designer's Guide Community
Forum
Models in Minutes
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines. Aug 14th, 2018, 8:51pm
  HomeHelpSearchLoginRegisterPM to admin  
 
1  Design / Analog Design / combined Bipolar-MOSFET current mirror
 on: Today at 7:42am 
Started by bki | Post by bki
Hi everybody,

i was wondering what happens if i Combine a PMOS current mirror  (source connected to VDD) with a PNP current mirror (Collectors connected to the PMOS Drains) instead of a full PMOS cascode current mirror?

Does (PMOS current mirror with PNP current mirror connected as Cascode configuration) make sense to do it and does it bring any benefits compared to a full PMOS Cascode Current Mirror?

Thank you!


2  Design / High-Speed I/O Design / How to simulate Differential return loss SDD, and Common mode return loss SCC
 on: Aug 12th, 2018, 9:31pm 
Started by darkhorse | Post by darkhorse
Hello everyone,

Is there anyone having guide or test bench sample to simulate SDD, SCC of the transmitter (driver) or receiver front end (RXAFE, CTLE), would you please share me?

Thank you.

3  Design / Analog Design / Re: Tow stage Op-Amp common mode feedback
 on: Aug 12th, 2018, 3:10am 
Started by Majid | Post by vroy_92
No you don't need two common mode feedback circuits. For example, consider the attached image. The block at the bottom of the circuit is your common mode feedback amplifier. It senses the CM of the output of the second stage and tunes the current of the first stage.

The common mode of the o/p of first stage cannot be fixed as it would still not fix your problem, and you will need to have another CMFB for your output stage. CMFB amplifiers are mighty hard to stabilise, and I never liked going for two of them.

Also the second stage typically has a much larger current than the first stage. For reasonable voltage swings at the output, your devices have to be sized such that they have a small vdsat, which means that the gm of the current source load of your second stage will be high. This will make it hard to stabilize your CMFB loop. [also you lose the advantage of having the Miller pole that can help you stabilise the CMFB loop]

4  Simulators / Logic Simulators / Re: how to include a module in another module?
 on: Aug 10th, 2018, 4:50am 
Started by liletian | Post by Andrew Beckett
You cannot nest modules in the Verilog standard. The SystemVerilog standard does allow nesting of modules, but the Cadence simulators do not currently support this.

However, I rather doubt you need it. I'm not sure what benefit embedding the comparator within test_module brings  you, since the comparator is not instantiated within test_module. Even if it was instantiated, there's no need to include one file in the other - you can just pass all the files to the simulator and it will compile them all, and elaboration will take care of linking them all together.

Regards,

Andrew.

5  Simulators / Logic Simulators / how to include a module in another module?
 on: Aug 9th, 2018, 10:10am 
Started by liletian | Post by liletian
 Hi all

 I wrote the following code (comparator.v and test_module.v), test_module is fairly simple. It just try to include comparator.v.

 However, when I try to compile the test_module.v, it reports the following errors. Can anyone help on the issue? Basically I am trying to include sub module using command "include", but I seems to have trouble on it.

 Thank you very much.

 ncverilog(64): 15.20-s022: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
file: test_module.v
module comparator(stag,ptag,tag_equal);
    |
ncvlog: *E,EXPENM (comparator.v,1|5): expecting the keyword 'endmodule' [12.1(IEEE)].
(`include file: comparator.v line 1, file: test_module.v line 2)
       module worklib.test_module:v
               errors: 1, warnings: 0
endmodule // test_module
       |
ncvlog: *E,EXPMPA (test_module.v,3|8): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
       Total errors/warnings found outside modules and primitives:
               errors: 1, warnings: 0
ncverilog: *E,VLGERR: An error occurred during parsing.  Review the log file for errors with the code *E and fix those identified problems to proceed.  Exiting with code (status 1).



test_module.v

module test_module();
`include "comparator.v"
endmodule // test_module


 comparator.v

module comparator(stag,ptag,tag_equal);
  parameter n=16;
  input [n-1:0] stag,ptag;
 
  output        tag_equal;

  reg           tag_equal;
 
  integer       i;

//   initial begin
//   tag_equal<=1'b1;
//   end
 
  always @(stag or ptag)
 
    tag_equal=!(stag^ptag);

endmodule

6  Simulators / Logic Simulators / Re: how to print integer in the verilog module
 on: Aug 9th, 2018, 4:26am 
Started by liletian | Post by Andrew Beckett
It works for me (using XCELIUM 18.10). I suspect that your problem is that you're only seeing the final value of i at each time - that's because the for loop increments i at the same time, with no delay - and $monitor outputs only the final value. From the IEEE 1364-2001 LRM (section 17.1):

Quote:
When a $monitor task is invoked with one or more arguments, the simulator sets up a mechanism whereby each time a variable or an expression in the argument list changes value—with the exception of the $time, $stime or $realtime system functions—the entire argument list is displayed at the end of the time step as if reported by the $display task. If two or more arguments change value at the same time, only one display is produced that shows the new values.


If (for example) I add a delay:

Code:
#1 if((stag[i]^ptag[i]))  



and then also change the final #10 to a #20 to allow sufficient time for the loop to complete, I then get:

        0 stag=xxxx,ptag=xxxx,tag_equal=x, i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
       10 stag=000a,ptag=000b,tag_equal=x, i=00000000000000000000000000001111
       11 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000001110
       12 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000001101
       13 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000001100
       14 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000001011
       15 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000001010
       16 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000001001
       17 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000001000
       18 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000000111
       19 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000000110
       20 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000000101
       21 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000000100
       22 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000000011
       23 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000000010
       24 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000000001
       25 stag=000a,ptag=000b,tag_equal=1, i=00000000000000000000000000000000
       26 stag=000a,ptag=000b,tag_equal=0, i=11111111111111111111111111111111
       30 stag=000b,ptag=000b,tag_equal=0, i=00000000000000000000000000001111
       31 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000001110
       32 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000001101
       33 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000001100
       34 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000001011
       35 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000001010
       36 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000001001
       37 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000001000
       38 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000000111
       39 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000000110
       40 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000000101
       41 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000000100
       42 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000000011
       43 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000000010
       44 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000000001
       45 stag=000b,ptag=000b,tag_equal=1, i=00000000000000000000000000000000
       46 stag=000b,ptag=000b,tag_equal=1, i=11111111111111111111111111111111


Regards,

Andrew.


7  Simulators / Logic Simulators / how to print integer in the verilog module
 on: Aug 8th, 2018, 10:34am 
Started by liletian | Post by liletian
Hi All

I write the following module comparator, In the testbench, I would like to monitor integer i, when I try to print out the interger using the following statement, it does not work. Is there a way to keep track of the interger in the testbench?

Thank you very much,



module comparator(stag,ptag,tag_equal);
parameter n=16;
input [n-1:0] stag,ptag;

output tag_equal;

reg tag_equal;

integer i;

// initial begin
// tag_equal<=1'b1;
// end

always @(stag or ptag)
for(i=n-1;i>=0;i=i-1)
begin: sweep
if((stag[i]^ptag[i]))
begin
tag_equal<=1'b0;
// break;

// disable sweep;
end
else tag_equal<=1'b1;
end
endmodule


module test_comparator();

parameter n=16;

reg [n-1:0] A,B;

wire tag_equal;

comparator #(n) com(.stag(A),.ptag(B),.tag_equal(tag_equal));

initial begin

$monitor($stime, " stag=%h,ptag=%h,tag_equal=%b, i=%b", A,B,tag_equal,com.i);

#10;

A=16'h000A;
B=16'h000B;

#10;
A=16'h000B;
B=16'h000B;
end // initial begin
endmodule

8  Other CAD Tools / Entry Tools / DRC error for Nwell resistor in UMC 130
 on: Aug 8th, 2018, 5:46am 
Started by abhilash_172 | Post by abhilash_172
Hi everyone,

when i look at the layout of the pcell ,there is space between the last contact on one terminal and edge of diffusion, but when i load that instance in layout , the last contact is appearing at the edge of diffusion, DRC is giving a min space error.
i checked for NMOS and PMOS, layout is same as pcell. Did anyone face this issue before ?
i uploaded the pic below.

Regards
Abhilash

9  Simulators / Circuit Simulators / Re: Vertical Bathtub Curve in Cadence ViVA
 on: Aug 7th, 2018, 6:16am 
Started by cheap_salary | Post by Andrew Beckett
Not currently. It's a good suggestion though - could you please contact Cadence Customer Support so that we can plan this enhancement with R&D?

Regards,

Andrew.

10  Simulators / Circuit Simulators / Vertical Bathtub Curve in Cadence ViVA
 on: Aug 7th, 2018, 3:50am 
Started by cheap_salary | Post by cheap_salary
We can plot Timing Bathtub Curve, that is, Horizontal Bathtub Curve from Eye Diagram in recent Cadence ViVA.
Here eyeBERLeftApprox() and eyeBERRightApprox() are available for this purpose.

However we also have to plot Amplitude Bathtub Curve, that is, Vertical Bathtub Curve.

And we need BER Contour Plot.

How can I plot Vertical Bathtub Curve and BER Contour Plot in Cadence ViVA ?

Attached figure is a result of Keysight ADS.
Actual Instruments also support Both Horizontal and Vertical Bathtub Curves, BER Contour Plot.

Trouble viewing this site? Copyright © 2002-2018 Designer's Guide Consulting. 'Designer's Guide' is a registered trademark of Designer's Guide LLC. All rights reserved.

Our colleges are not as safe as they seem. Sexual assault is pervasive and the treatment of the victim by the adminstration is often as damaging as the assault: Campus Survivors, Campus Survivors Forum.

Some of our other sites that you might find useful: Avendesora, Inform and QuantiPhy.