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1  Design / RF Design / basic LNA power related doubt
 on: Yesterday at 11:30pm 
Started by ezekiel1983 | Post by ezekiel1983
I am a mixed signal engineer .
i am trying to learn RF
Can you please help me with 2 doubts for which i was not able to see any answer anywhere.

is my assumption right that an LNA or an PA crossing P1db  due to an input drive, saturate eventually and start clipping the o/p waveform like normal opamp based amplifiers ..
in that case if the LNA is hard saturated by a CW of lets say 1616 Mhz  can it still amplify a 1600Mhz component of lets say -120dbm..
i understand if the modulation is phase or frequency ..a saturated amp may still help convey message ..but the point is what if the saturation is because of  different spectral component (in our case 1616 Mhz)and we are talking about demodulating a different carrier (in this case 1600Mhz)

The second one

AV02-2812EN DS MGA-22103 28Jun2011

MGA-22103 2.5-2.7 GHz WiMAX Power Amplifi er Module Data Sheet Description Avago Technologies MGA-22103 power amplifi er module is designed for mobile and fi xed ...

for the above part which operates from 3.3 volts ,p1db of 31dbm is claimed on datasheet  to a 50ohm load ..that would mean the voltage is about 22 volt peak to is this possible as drive power is only 3.3 volts

other than  a resonant amplier with high q how are they achieving this ?

Is there any class of operation which can do this ?



2  Design / RF Design / saturated operation of LNA
 on: Yesterday at 11:28pm 
Started by ezekiel1983 | Post by ezekiel1983
Part in discussion :TQP3M9007
Area of doubt :saturated operation of LNA

If a combined signal of 1616 Mhz  18 dbm CW along with -130dbm 1575  Mhz CW is being given at the input of the part in discussion fed with a 5 volt  supply
1.      What gain could I get for the 1575 component?
2.      Is the compression after p1db based on attack release method ,in which case please provide attack and release time .
3.      If not and it is based on instantaneous power (soft clipping) then is the understanding correct that the o/p slowly  starts clipping towards a square wave  waveform with rounded edges and as power level goes high from about 12.5dbm input  it goes more squarer .in which case I may not reproduce (the phase ,frequency info )the 1575 correctly as during the squarer part of the o/p waveform there isnít any 1575 information making through .The 1616 component will still pass through the frequency and phase information with some degradation on the amplitude information.
4.      Will the LNA take time to regain its active operation from a saturated state ?if yes how much in my case ?
5.      Can you please explain the saturation mode operation little detailed for the above part ?


3  Simulators / Circuit Simulators / Re: AMS simulator multi threading
 on: Yesterday at 12:11pm 
Started by subtr | Post by subtr
Could you please tell me as to a information you require?

4  Simulators / Circuit Simulators / Re: AMS simulator multi threading
 on: Yesterday at 7:03am 
Started by subtr | Post by Andrew Beckett
There are many things that could be the problem here. Maybe your connect modules have excessively fast rise/fall times and that is causing the timestep to collapse in the simulation? It's going to be very hard to diagnose without more information, I'm afraid.


5  Simulators / Circuit Simulators / Re: AMS simulator multi threading
 on: Yesterday at 5:10am 
Started by subtr | Post by subtr
Hi Andrew,
The thing is that my simulations are fast enough without any transistors or such pdk elements. Even verilogA, AnalogLib, ahdllib components don't slow down. The moment I put two inverters, the simulation becomes like hundred times slower. I would like to know if the problem is genuine and if there's a way out. To speed up. What could be the cause? Sad

6  Design / Analog Design / A Question regarding Ft of a technology node
 on: Mar 25th, 2017, 10:37pm 
Started by iVenky | Post by iVenky

I have a question regarding 'ft' shown below

I would be happy if you could answer me the question.

7  Simulators / RF Simulators / Moved: Substrate parameters values?!!!
 on: Mar 25th, 2017, 2:49am 
Started by Hamid1982 | Post by Hamid1982
This Topic has been moved to Physical Verification, Extraction and Analysis by Ken Kundert.

8  Other CAD Tools / Physical Verification, Extraction and Analysis / Substrate parameters values?!!!
 on: Mar 25th, 2017, 2:49am 
Started by Hamid1982 | Post by Hamid1982
Hi to All,

How I can know(extract) the following values of substrate parameters(mju, Eox,toxM1M2, tox, t, conductivity) ​​from the figures of this substrate example (see attached file)???

I need to your help please.


9  Other CAD Tools / Physical Verification, Extraction and Analysis / Re: cmos active inductor......
 on: Mar 25th, 2017, 2:31am 
Started by ofaruqe20 | Post by Andrew Beckett
You'll need to provide some context. This is the kind of information you'll need to provide to allow anyone to help:

  • What does the circuit look like that you're analysing (pictures or even better a netlist would be good)
  • You posted this in the physical verification and extraction forum, so what tool are you using to extract the circuit?
  • What simulator and version are you using?
  • How are you simulating this? What analysis, what setup?
  • What do the results look like that you think are problematic?

Your question as it stands is too lacking in detail to be able to answer, other than me suggesting you speak to your supervisor...


10  Design Languages / Verilog-AMS / Re: Loop filter Verilog AMS
 on: Mar 24th, 2017, 11:59pm 
Started by JeromeONeill | Post by Ken Kundert
If you put V(p,n) <+ 0, doesn't that short out everything else in the module?

No. It shorts nodes p and n, which essentially makes nodes p and n aliases of each other, but the capacitors and resistors are connecting from p/n to ground, those are not shorted.

In general, I prefer not to use simulator primitives because they are very static. Specifically you cannot change their parameter values with time. I like the ability to do that. That may not be helpful in this situation, but it is really helpful in testbenches.


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