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1  Design / Analog Design / Re: How to design a PLL with a cycle to cycle jitter under 300ps? how to simulate?
 on: Yesterday at 9:37pm 
Started by hezea | Post by hezea
thangks for your answer, I have a question recently, what is the relationship between the period_jitter and cycle to cycle jitter? Is it the 1.414 times relationship ?

2  Simulators / Circuit Simulators / Analog signal conditioning circuit design
 on: Yesterday at 3:02pm 
Started by v2h | Post by v2h
Hello everyone,

I want to design an analog signal conditioning circuit for an application. I have a photo multiplier tube and its light output is converted to an analog signal using a voltage divider. The application is to digitize the analog signal. Could you anyone please suggest a good source where I can start to implement this design?

Thank you.

3  Simulators / Circuit Simulators / Re: Eldo noisetran Problem on Fully Diff. Amp
 on: Yesterday at 2:54pm 
Started by gcorrig | Post by monglebest
May I know is the equation right?
2*((7nV/rt.Hz)^2*GBW*Pi/2)^1/2 = 108uV

I thought it should be *f(3dB BW) instead of *GBW.

4  Design / Analog Design / Chopping inside or outside the feedback loop?
 on: Sep 22nd, 2017, 11:14pm 
Started by jdp | Post by jdp

We know of two possible configurations in which the chopper-switches can be placed to realize a chopper stabilized amplifier - either outside the negative feedback loop, or inside the loop (as shown in figure below).

What are the advantage and disadvantage of either of these schemes?

Any relevant reference/paper is also appreciated.

Thank you!

5  Simulators / Circuit Simulators / Re: LC VCO Simulation Help needed !!
 on: Sep 22nd, 2017, 8:59pm 
Started by umberabbas | Post by cheap_salary
umberabbas wrote on Sep 22nd, 2017, 4:17am:
I did the same as Ken specified.
You invoke supply voltage pertubation(step pulse) for kicking oscillator start up.

You don't set "maxstep" in previous netlist.

Now you set "mastep=(1/60G*20)" and "method=trap" in new netlist.

However I don't think your oscillator work with your netlist, since you set "delay=2" in V1.

I think "delay" is around 5nsec.
Show us true netlist.

Geoffrey_Coram wrote on Sep 22nd, 2017, 4:47am:
umberabbas wrote on Sep 19th, 2017, 8:01pm:
I have removed V0 ....
But I still see
V0 (vdd! 0) vsource dc=1 type=dc
in the screen-shot.
"vdd!" is a lonley node.

6  Simulators / RF Simulators / Re: Comparator ISF using PSS/PAC
 on: Sep 22nd, 2017, 4:00pm 
Started by kerekuto | Post by sheldon
If you have access to the IEEEXplore, you can probably still find the

Be aware that the measurement is non-trivial even in simulation. There
are simpler methods based on frequency domain simulations.

7  Simulators / RF Simulators / Re: PLL Phase Noise Simulation
 on: Sep 22nd, 2017, 3:58pm 
Started by Count | Post by sheldon

  The calculation is more complex. You actually perform a power spectral
density on the absolute jitter. An FFT is good measuring distortion, the
power spectral density is used for measuring noise. See the PLL modeling
white paper for a detail discussion on the topic.

8  Simulators / RF Simulators / Re: Transistor Width vs Noise Figure Curve
 on: Sep 22nd, 2017, 3:55pm 
Started by umberabbas | Post by sheldon

     One option would be to use the test bench in
for Noise Figure measurements, select NF on the menu. Then run a parametric analysis sweeping the width of the device.


9  Simulators / RF Simulators / Re: Is it possible to use QPSS and QPNoise to simulate the jitter in SpectreRF?
 on: Sep 22nd, 2017, 3:45pm 
Started by Jacki | Post by sheldon

   QPSS can't be applied to this problem. The oscillator is a driven circuit,
while the power supply is being driven. Mixing autonomous and driven
periodic state simulation is not supported in QPSS, as I remember.

There are several options:
1) Create a PWL source of your noise and perform a transient analysis
   of the oscillator. There is an example, of using this approach for a
   driven circuit in ADC RAK. The example shows the jitter calculation
   for an ADC clock driver due to switching power supply noise on VDD.
2) Try semi-autonomous analysis, there is limited support for mixed
   autonomous-driven support in Harmonic Balance analysis. Not sure
   if it works with jitter analysis so you may need to manually do the
   jitter calculation.


10  Design / Analog Design / Re: Deriving Gm of circuit
 on: Sep 22nd, 2017, 3:33pm 
Started by blue111 | Post by sheldon
In general, if the gm stage is capacitively loaded, then the input voltage
should be Output Voltage Excursion/ open loop gain at frequency. So,
the effectively signal levels for the input devices should be small.

In general, the gm of a gm-C filter stage has some method of fixing the
gm to a constant value across the operating range. If it isn't then there
is distortion, that is, the gm changing as a function of input signal level
causes limits the dynamic range of the stage. The function of the source
degeneration resistors in the original schematic is region where the gm
in constant.

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