1 
General / Tech Talk / It's SiP (still) a trend today?
on: Oct 18^{th}, 2018, 7:26pm 
Started by kalinski  Post by kalinski 
Hi everyone!
I'm thinking of developing SiP in my master thesis, it has new industry releases almost every day, what would you think that would be an interesting case: an IoT SiP module or a SiP Power Management? It's a real trend or tend to dissipate fast? And somebody has a suggestion for literature on this topic (SiP/Package design)?
Thank you! 

2 
Design / Analog Design / How to understand "kTC" noise?
on: Oct 18^{th}, 2018, 6:06am 
Started by A Kumar R  Post by A Kumar R 
Hi,
I have been going through noise fundamentals and while i was reading about "kTC" noise...they say it is independent of resistor. To some extant this is understandable because the resistor noise is white (meaning uniform across all frequencies) and only C has to play a role to band limit the noise.
what surprises me is that the final equation (you can find this in Razavi noise chapter also), which is sqrt(kT/C) when integrated from 0 to infinity, gives much less noise than you would otherwise get if you were to sum each noise voltage at each frequency in that 0 to infinity band.
i have understood the math of this, but, qualitatively not getting it.
one more thing, when a circuit gives complex impedance at its two ports, then the thermal noise is calculated by looking at the real part of this complex impedance.
my question is that the real part you would get is not physically present in the circuit wheras the noise will be generated from physical resistor right?
why is this so?
Thanks, Kumar R 

3 
Design / Analog Design / General method for phaselocked loop filter analysis and design
on: Oct 16^{th}, 2018, 9:09pm 
Started by blue111  Post by blue111 
For this http://scihub.tw/https://ieeexplore.ieee.org/document/4490229 General method for phaselocked loop filter analysis and design paper , I have few questions: 1) In section 3 Classification for PLLs , could anyone help to explain on this ? and how to derive this frequency rolloff expression ? Quote:The difference between order and type gives a measure of the ability to filter out highfrequency phase noise contribution, in such a way that the highfrequency rolloff is given by the expression: 6.02 * (order – type + 1) dB/octave. 2) Could anyone prove mathematically that "The order needs to be higher than type only when extra attenuation of phase noise is needed" ? 3) Besides, could anyone derive expression (7) ? and how does this inequality expression guarantee that the transient and filtering capabilities of the PLL is unchanged while increasing the hold range (which is proportional to K_pv, according to author ? ) ? 4) For Floyd Gardner's Phaselock Techniques 3rd edition book, how do we derive stability criterion inequality for type 3 digital PLL which is expression (4.23) ? 

4 
Design / Analog Design / Re: PMOS current source IV characteristics
on: Oct 15^{th}, 2018, 11:23am 
Started by Harian  Post by Nyquist 
Hi Harian,
you have connected gate to a constant voltage and swept the Source voltage. In effect, you are actually sweeping VSG and plotting the Source current. The plot looks correct.
If you need to plot the IDVDS Characteristics, then you need to connect a voltage source between Source and Gate (VSG). Now you can sweep VSD for different values of VSG to get the plot you want.
Nyquist 

7 
Design / Analog Design / what are these two circuits?
on: Oct 11^{th}, 2018, 1:25pm 
Started by alan kim  Post by alan kim 
What are this circuit? It looks like some sort of current mirrors but I am trying to understand what it is and what the merits/drawback of it. Has anyone seen this before? Appreciate that you share your experience! 

