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1  Design / Mixed-Signal Design / Re: VCO based ADC frequency domain behaviour
 on: Apr 18th, 2018, 3:50pm 
Started by polyam | Post by polyam
Freq. res. of VCO-ADC

2  Design / Mixed-Signal Design / VCO based ADC frequency domain behaviour
 on: Apr 18th, 2018, 3:50pm 
Started by polyam | Post by polyam

I am interested in doing a proper simulation in Spectre to extract the frequency response of a VCO-based ADC. Please check the following figures. A VCO based ADC can be modeled as an integrator followed by a sampler and a differentiator. Can anyone help me to do a simulation in order to get the following curves?  It is expected to have a low pass behavior at the output of VCO (let's say ring oscillator). Such a low-pass behavior must be canceled by the frequency response of the differentiator resulting in a flat frequency response. my target is to reproduce such a figure in Spectre.
BTW these figures come from "Design of a 5bit 1GSps VCO Quantizer for a CT Delta Sigma Modulator"

tnx  :)

3  Modeling / Semiconductor Devices / Should I use an optocoupler here?
 on: Apr 18th, 2018, 1:56am 
Started by sunrise7747 | Post by sunrise7747
HI everyone,

I have finally succeded in making a decent DC to DC converter. A this point, I am only testing how fast I can charge a cap to 300V. To discharge it, I am using a SCR. This got me thinking....I may need more protection.
In my current, I have 2 connections from my pic that controls the charging pulse and the discharge of the secondary.
1. The transistor that controls the primary switching is a logic level mosfet. I used this so I could easlily switch my 12v rail with no extra parts. I have a winding ratio of 1:10, so in event of current production from the secondary to the primary, the mosfet will only see 30V and it is rated to 100V.
-In this case, is an optocoupler needed?
-should I place a zenner from the gate to the drain?
2. The other transistor is the SCR that discharges the 300v cap on the secondary side. So far, I have been just using a resistor to a 5v signal to open it and discharge. I need to control this with a pic pin.
-Should I use an optocoupler here?
I may have some questions about optocouplers themselves though i have checked out the opto basics and learned how Opto works (maybe you haven't checked out something like this, so you could pick up here:, I know opto are often used for physical separation of the control signals of the power circuit and are always welcome. I have some here, but online circuits look a little odd to me.

I bought some high speed optocouplers. They are the 6n137 models. They are 2 channel also, so that will be perfect. I am using the NTE2987, as mentioned earlier .However, the other transistor is the 2n6504 SCR...and I am getting quit irritated with this. First of all, it looks like I am going to need a SCR dedicated optocoupler. Second, I am disappointed with it getting stuck in the on state because of my highly inductive load. And third...Im not using AC current, so I dont think the SCR is necessary. I am discharging 300V and 480uF, which comes to around 20J of energy. Can you also recommend a non-scr transistor to discharge a high voltage? I have some IRF730 units here. They are rated at 400V...but the single pulse avalanche rating says I dont know if this will blow her.

Thanks a lot in advance!

4  Design / RF Design / PLL design questions
 on: Apr 17th, 2018, 3:51pm 
Started by maxcy | Post by maxcy
Newby here. Where would I post and see topics that relate to PLL Design questions? As I would like to post questions regarding the PLL Design Assistant.

5  Design / High-Speed I/O Design / Re: Quantifying Eye Diagram for high-speed SERDES channel
 on: Apr 17th, 2018, 2:46pm 
Started by aguntuk | Post by repah

(copy whole link and put in browser)

6  Design / Analog Design / Re: How to compensate the parasitic cap of the top plate of DAC in SARADC
 on: Apr 17th, 2018, 2:44pm 
Started by Jacki | Post by DanielLam
1) Use a top-plate sampling SAR ADC.
2) Make your caps better so that you don't have that much top-plate parasitic (7%) is quite high.
3) Have an adjustable reference. You kind of need this in practice.

7  Design / High-Speed I/O Design / Re: State-of-the-art speed for high-speed electrical channel
 on: Apr 17th, 2018, 2:44pm 
Started by aguntuk | Post by repah
Read these two papers:

Historical Trends in Wireline Communications: 60? Improvement in Speed in 20 Years, Behzad Razavi

Looking to the Future: Projected Requirements for Wireline Communications Technology, Hirotaka Tamura

8  Design / High-Speed I/O Design / Re: relation between CMOS technology and speed of I/O
 on: Apr 17th, 2018, 2:41pm 
Started by aguntuk | Post by repah
Without design innovations, the achievable operation frequency
of circuits is around fT /10. With some design innovations
it is possible to design circuits up to fT /4 or in some cases ft/2.

See paper:

Process and device requirements for mixed-signal integrated circuits in broadband networking

This is just a guide, not a general rule.

9  Design / Analog Design / Fully Differential Amplifier MISMATCH analysis
 on: Apr 17th, 2018, 2:56am 
Started by Ankit | Post by Ankit
Hi all,

I am designing two stage fully differential amplifier. Both stage are CMFB compensated. My problem is that after first stage only there is so much offset in output of first stage (because of mismatch) Second stage ouputs are going to vdd and ground.

Is there any solution to it.

Please find the ckt image attached.

Waiting for reply urgently.


10  Design / Analog Design / Re: How to compensate the parasitic cap of the top plate of DAC in SARADC
 on: Apr 17th, 2018, 1:34am 
Started by Jacki | Post by Jacki
I think I can end my thread. Maybe just accept the gain drop, keep the resolution, and compensate the parasitics as much as possible by the custom designed MOM cap.

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