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1  Design / High-Power Design / Re: LDMOS in DNW
 on: Yesterday at 12:40pm 
Started by neoflash | Post by Horror Vacui
I see no theoretical obstacles, that's why you have DNW in the technology. What is the source of your doubt? If you run a simulation with the most equipped model and spectre throws an assert/warning about it, than it has a reason. People has taken extra efforts to add these checks into the model file. Especially if the model maturity is high.

2  Simulators / Circuit Simulators / Re: Coomon Mode Feedback
 on: Yesterday at 12:35pm 
Started by Majid | Post by Horror Vacui
Basically any Smiley, but I would suggest transient and stb.

3  Design Languages / Verilog-AMS / Re: SKILL functions in VerilogA possible?
 on: Yesterday at 12:33pm 
Started by Horror Vacui | Post by Horror Vacui
I do not need to do this, I just found the idea of saving the already post-processed simulation results from a verilogA module promising.

I have a verilogA block which does my sweep control for two variables and writes the results into a textfile, from where I can plot the necessary data. Otherwise I should run too many spectre runs, where most of the runs will not have a meaningful result (=the circuit can not function as intended). One of the simulation results are what is the range where the circuit operates. I find it non trivial to let it plot in Cadence, but I find it very easy to just write it into a text file. Since I have to write into a file the idea emerged that I could add another data to it as well.

One of the problem is that the output text file where I save the results from the verilogA module, takes its filename from the block properties. I run the same testbench with different config views, with and without parasitic extraction.
It would be a great help if I could change some things in the outputs, what I have to write manually before every run if something changes: output filename, what config view has been run, which LPE view has been used, which corner is it on, date, because it might change after copying, but I could think of another information to archive.
It does not need to be SKILL, it can be anything, C, Fortran, Pascal, Java, I just wondered whether it is possible.

4  Simulators / Circuit Simulators / Re: Spectre convergence issues device loading failed
 on: Yesterday at 3:27am 
Started by SureshCh | Post by Andrew Beckett
You may be best contacting Cadence Customer Support at http://support.cadence.com so that an Application Engineer can look in detail at your problem by being able to see the netlist and models.

Regards,

Andrew.

5  Design Languages / Verilog-AMS / Re: SKILL functions in VerilogA possible?
 on: Yesterday at 3:23am 
Started by Horror Vacui | Post by Andrew Beckett
It's not that clear quite what you're trying to achieve here or why you need SKILL to do it. You could write a custom netlisting procedure, but I can't give that much advice without a clear example of what you want or what needs to be done at netlisting time.

Maybe this would be better handled by a question to Cadence Customer Support at http://support.cadence.com

Regards,

Andrew.

6  Design / High-Power Design / Re: LDMOS in DNW
 on: Jun 15th, 2018, 8:43am 
Started by neoflash | Post by Geoffrey_Coram
That's probably proprietary information that the foundry won't want on a public web site. You should probably contact the foundry (or read the documentation for whatever process it is that you're using).

7  Design / Mixed-Signal Design / Moved: Coomon Mode Feedback
 on: Jun 14th, 2018, 7:30am 
Started by Majid | Post by Majid
This Topic has been moved to Circuit Simulators by Ken Kundert.

8  Simulators / Circuit Simulators / Coomon Mode Feedback
 on: Jun 14th, 2018, 7:30am 
Started by Majid | Post by Majid
Hello everybody

Which kind of analysis should I use to check if a common mode feedback circuit works or not ?

9  Design / Analog Design / Moved: DC/Dc step up converter
 on: Jun 13th, 2018, 6:09am 
Started by ouijdane | Post by ouijdane
This Topic has been moved to Verilog-AMS by Ken Kundert.

10  Design Languages / Verilog-AMS / DC/Dc step up converter
 on: Jun 13th, 2018, 6:09am 
Started by ouijdane | Post by ouijdane
Hello,

I'm a beginner in verilog a modeling, I want de modelize a DC/DC step up converter with PFM fixed on time and I don't have any idea about how should I process.

Could you help me please?
Regards,

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