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1  Modeling / Passive Devices / Need some assistance in identifying potential cause for this noise
 on: Yesterday at 7:26pm 
Started by Tovelo | Post by Tovelo
I have a CS4270 codec hooked up to a Raspberry Pi more or less according to the "recommended layout" in the datasheet , shown below. This device sinks power from three different places (VA = power for analog subcircuits, VD = power for DSP, VLC = power for control port (I2C and clocks). Currently VA is sourced by an LT1965 (in turn powered from an Adafruit Powerboost connected to a LiPo battery) while VLC and VD are sourced from the Raspberry Pi's 3.3V output.


I am able to record from the device as expected using SoX on or arecord on the Pi, however I am confronted with a troubling amount of noise on the signal. These images are representative of what I'm seeing:

Full spectrum, 0-96kHz



Bottom of the spectrum, about 0-1kHz


In the top spectrogram, I see spikes of broadband noise repeating at about 33.3Hz, though the exact period seems to vary from recording to recording (I just saw some at about 50Hz in another recording). In the bottom spectrogram, I see narrowband noise at 50-60Hz and some bad harmonics. I haven't even started work on the signal chain leading into the ADC yet because these artifacts are everywhere on the board — I've plugged the inputs into ground, VA/2, even the codec's own midpoint reference voltage (VQ) and I see the same kind of thing everywhere, albeit with varying levels of intensity.

Clearly, 60Hz harmonics screams noise from the power main, but the whole setup is disconnected entirely from the wall (powered by battery at the moment).

Here's a shot of my actual current layout. In this case the ADC inputs are tied to VA / 2 through a simple passive filter(a complete introduction about passive filter:http://www.apogeeweb.net/article/36.html) (lower board), which in an ideal world would produce a bunch of zeroes on the ADC. The LT1965 is powered through a filter with a few decades' worth of caps and a ferrite bead — not strictly necessary but it did seem to help with actual mains noise. These particulars aren't super relevant since varying the power source or the input still results in the same artifacts.



I would really, really appreciate some assistance in identifying potential culprits for this noise. Is this something characteristic of the topology? Or is this to be expected on a $1 Chinese breadboard with jumpers everywhere, and I should just order a PCB with the same layout for further testing? Obviously this is difficult to debug remotely — my hope is that someone will see this and say, "aha! I've seen this before!"


2  Measurements / RF Measurements / Plotting 4 UI eyes
 on: Yesterday at 12:01pm 
Started by iVenky | Post by iVenky
Hi,

I have a scope that has a built-in CDR. It plots eye for 1UI. I wish to plot multiple eyes to see the effect of SJ etc., like I want to plot 4 UIs. Is there a way to do that generally with a built-in CDR? (I know it's possible when we have an external reference clock).

Regards,
Venkat

3  Design / Mixed-Technology Design / Re: Making wiress pulse transmitter, can use some help
 on: Yesterday at 11:57am 
Started by evan123 | Post by evan123
Learn cool electronic Circuits like FM Transmitter Circuit and solar battery charger. Also Learn other things like types of transistor and difference between microprocessor and microcontroller in a very simple way.

4  General / Tech Talk / Variable Power Supply
 on: Yesterday at 9:05am 
Started by SATCOM | Post by SATCOM
I am looking to either purchase or make a power supply that has the following;
1.   One to three outputs.
2.   Each output will be independent and variable form 0-28vdc with a max current of three amps
3.   Would like to be able to have digital display of current and voltage.

Next I am looking to purchase or design something that would possibly interface with a laptop.  It would be nice for the laptop to be able to control the voltage adjustment.

I would also like for the laptop top be able to record the current draw an voltage and then be able to play it back on the laptop and plot the draw.

My purpose for this is to hook it up to an antenna, each power supply will be hooked up to a motor, there is a train motor that goes 360 degrees, there is an elevation motor that goes from -90 to +120 and there is a Cross Level motor that goes from like -90 to + 90.

Thank you in advance for your help

5  Design / RF Design / calculation of total width of MOS using finger width and multiplier
 on: Yesterday at 2:42am 
Started by Sagar Juneja | Post by Sagar Juneja
If we are given a finger width, numbers of fingers and multiplier then as per my understanding the total width of MOS = finger_width*number_of_fingers*multiplier.

Is my understanding correct? I refereed  to one sample circuit in cadence manual, i am not been able to understand how they have calculated the total width. Screenshot is attached.

6  Design / RF Design / Re: getting incorrect s-parameters (S21 & S12) for LNA design
 on: Jan 17th, 2018, 10:31pm 
Started by Sagar Juneja | Post by anonymus
I attached a pdf here which might help you, because the deign is looking similar check it once.

7  Design / RF Design / low noise amplifier with active inductors
 on: Jan 17th, 2018, 10:20pm 
Started by anonymus | Post by anonymus
Hello all,

I'm designing an Low noise amplifier with active inductor for 2.4 GHz with 180nm tech, i want to replace the inductors present in the lna designed  earlier with active inductors.
1)what is the maximum inductance value that could be achieved with active inductors?
2)what could be the better choice of active inductor that is connected to VDD having a value of 5.4 nH and an inductor connected between 2 mosfets having a value of 7.57 nH?

Here i attached the partial circuit where i want to repalce the inductors


Thank you

8  Design / High-Power Design / How to do AC simulation for constant on time buck converter in Simplis
 on: Jan 17th, 2018, 10:08pm 
Started by ttwwjj | Post by ttwwjj
Hi gus,

I am trying to do the stability analysis for a V2 control constant on time buck converter. The attachment is the circuit I used. The only difference here is I don't have an Error Amp, instead, I connect Vref directly to the comparator.

I do the ordinary AC simulation, the result is kind of weird. There is double pole on LC resonance freq, which should not be the case for constant on time control. Also DC gain increases with inductor value, which doesn't make any sense.

I wonder ordinary AC simulation in Simplis is suitable for this kind of pseudo fixed freq circuit? Should I use Multi-Tone AC Analysis as they introduce on their website? Haven't try that since I don't have the DVM license.

BTW, is it convenient to do stability analysis in Spetre using PSS and PSTB? Looks like most people prefer Simplis.

Thanks

9  Design / RF Design / getting incorrect s-parameters (S21 & S12) for LNA design
 on: Jan 17th, 2018, 9:29pm 
Started by Sagar Juneja | Post by Sagar Juneja
I am designing LNA for GPS (1.57Ghz), i am getting reasonable S11 and S22 = -10dB and -14dB respectively but my S21 is always coming as equal to S12 (i.e. S12 = S21 = -3dB).
Attached is my circuit.

Can somebody advise what could possibly be wrong.

I am designing using Cadence Virtuoso 180nm tool

10  Measurements / Phase Noise and Jitter Measurements / jitter vs center frequency
 on: Jan 17th, 2018, 7:50am 
Started by iVenky | Post by iVenky
Hi,

I am trying to measure the jitter of a clock signal by sending through a transmitter using 11001100 pattern (fclk/2) and 1010 pattern (fclk).  First, the absolute RJ should be the same on both cases, right? Also, if I integrate the phase noise over a certain bandwidth, it should be the same in both the cases, right?

Also, I am seeing a mismatch in the jitter obtained from a scope (through histogram) and integrated jitter from spectrum analyzer. Is that possible?

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