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Modeling >> Behavioral Models >> verilog-a code delay and pulse width generation.
https://designers-guide.org/forum/YaBB.pl?num=1540504563

Message started by openloop on Oct 25^th, 2018, 2:56pm

Title: verilog-a code delay and pulse width generation.
Post by openloop on Oct 25^th, 2018, 2:56pm

I need to create some delays in my verilgo-A code to wait for inputs and to provide some time for outputs to occur, and I also want the code to output reasonable size pulses. My code is being used as a controller for some synchronous counters, etc. These things are going to want a reasonable pulse width to function. I have a clock available but have not used it yet in my code. Could someone give me some ideas on how this is done? Some code examples that I can learn from?
Verilog-A is a struggle for me.

Title: Re: verilog-a code delay and pulse width generation.
Post by Ken Kundert on Oct 27^th, 2018, 12:17am

You might want to look at the models on the Verilog-AMS page. Particularly the Verilog-A oscillator models.

-Ken