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Design Languages >> Verilog-AMS >> SKILL functions in VerilogA possible?
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Message started by Horror Vacui on Jun 1^st, 2018, 1:52am

Title: SKILL functions in VerilogA possible?
Post by Horror Vacui on Jun 1^st, 2018, 1:52am

Hi everyone,

I would like to give over some parameters to my verilogA block during netlisting (library/cell/cellview used for simulation, date, username, and if possible model section/corner o be used) so they could be written into the output file generated by the VerilogA module.
I sweep some parameters and measure a few important results in my circuit with VerilogA and create an output file. It is much faster and easier then using running parametric sweeps. Also a similar thing might be used for debugging purposes as well.

Is it possible at all? I fear it is not trivial. I have looked into /thought at the following:
- spectre runs independently from the Cadence environment in batch mode, so I do not think I can solve the problem there.
- The CDF callbacks are only evaluated when the Edit Properties form is used, which is not enough for me.
- netlister: On the other hand I am skeptical here as well. I believe that the netlister just grabs the database information - i.e. "strings" - from the devices and puts them into a netlist file as they were. At least if I would develop a netlister I would not complicate it more than necessary (KISS principle). A problem is that I do not know where is the netlister documentation.

I have no other ideas. Do you have any idea how to - try to - solve this?

Title: Re: SKILL functions in VerilogA possible?
Post by Andrew Beckett on Jun 2^nd, 2018, 6:47am

Not entirely sure whether this will help, but see this thread on the Cadence Community Forums:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/37847/detecting-process-corner-from-within-veriloga-model

Andrew.

Title: Re: SKILL functions in VerilogA possible?
Post by Horror Vacui on Jun 5^th, 2018, 1:23am

Hi Andrew,

Thanks for the link. It is an interesting one, and it could be a solution to a part of my problem.
Are you aware any general way that makes it possible to put the result of a SKILL function into the netlist?

Thanks,
Zoltan

Title: Re: SKILL functions in VerilogA possible?
Post by Andrew Beckett on Jun 17^th, 2018, 3:23am

It's not that clear quite what you're trying to achieve here or why you need SKILL to do it. You could write a custom netlisting procedure, but I can't give that much advice without a clear example of what you want or what needs to be done at netlisting time.

Maybe this would be better handled by a question to Cadence Customer Support at http://support.cadence.com

Regards,

Andrew.

Title: Re: SKILL functions in VerilogA possible?
Post by Horror Vacui on Jun 17^th, 2018, 12:33pm

I do not need to do this, I just found the idea of saving the already post-processed simulation results from a verilogA module promising.

I have a verilogA block which does my sweep control for two variables and writes the results into a textfile, from where I can plot the necessary data. Otherwise I should run too many spectre runs, where most of the runs will not have a meaningful result (=the circuit can not function as intended). One of the simulation results are what is the range where the circuit operates. I find it non trivial to let it plot in Cadence, but I find it very easy to just write it into a text file. Since I have to write into a file the idea emerged that I could add another data to it as well.

One of the problem is that the output text file where I save the results from the verilogA module, takes its filename from the block properties. I run the same testbench with different config views, with and without parasitic extraction.
It would be a great help if I could change some things in the outputs, what I have to write manually before every run if something changes: output filename, what config view has been run, which LPE view has been used, which corner is it on, date, because it might change after copying, but I could think of another information to archive.
It does not need to be SKILL, it can be anything, C, Fortran, Pascal, Java, I just wondered whether it is possible.

Title: Re: SKILL functions in VerilogA possible?
Post by Frank Wiedmann on Jun 19^th, 2018, 1:28am

Did you already take a look at the section "Special $fopen Formatting Commands" in the Cadence Verilog-A Language Reference (https://support.cadence.com/apex/techpubDocViewerPage?path=veriaref/veriaref17.1/chap9.html#1037960)?

Title: Re: SKILL functions in VerilogA possible?
Post by Horror Vacui on Jun 20^th, 2018, 2:07am

Yes, I looked at it at the beginning, but these formatting commands are just a limited set and they can be used only for filenames. They did not work when I wanted to write them into the file.