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Design >> Analog Design >> LDMOS 5V tolerance in 40nm with 3.3v oxide
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Message started by neoflash on Dec 2^nd, 2017, 8:11pm

Title: LDMOS 5V tolerance in 40nm with 3.3v oxide
Post by neoflash on Dec 2^nd, 2017, 8:11pm

Hi guys,

I have a question about 5V LDMOS on GF and TSMC 40LP process.

Lightly doped drain can increase the VDS tolerance greatly. However, oxide stress condition should not be improved by LDMOS structure.

How does 5V LDMOS with 3.3v oxide achieve VGD 5V tolerance in off state (VG=0, VD=5V)?

Regards,
Neo

Title: Re: LDMOS 5V tolerance in 40nm with 3.3v oxide
Post by Maks on Dec 19^th, 2017, 12:08am

Drain in LDMOS is located far away from the gate - it's separated by STI and by drift region, where a significant fraction of Vds drops.