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Design Languages >> Verilog-AMS >> Is there a way to implement this kind of RC model in veriloga?
https://designers-guide.org/forum/YaBB.pl?num=1512194498

Message started by ray0923 on Dec 1^st, 2017, 10:01pm

Title: Is there a way to implement this kind of RC model in veriloga?
Post by ray0923 on Dec 1^st, 2017, 10:01pm

I am trying to implement a resistor and a voltage dependent capacitor in series. I know i can use ddt to implement a voltage dependent capacitor but with resistor in series, the voltage drop on the capacitor is not really straight forward to derive. It seems recursive to me.

Title: Re: Is there a way to implement this kind of RC model in veriloga?
Post by Ken Kundert on Dec 1^st, 2017, 11:34pm

There are two ways of adding a series resistance. First, you can simply add an internal node and an additional branch. For example, consider this nonlinear capacitor

Code:

module varactor(p, n);
inout p, n;
electrical p, n;
parameter real c0 = 1p from (0:inf); // nominal capacitance (F)
parameter real c1 = 0.5p from [0:c0); // maximum capacitance change from nominal (F)
parameter real v0 = 0; // voltage for nominal capacitance (V)
parameter real v1 = 1 from (0:inf); // voltage change for maximum capacitance (V)
real q, v;
analog begin
v = V(p,n);
q = c0∗v + c1∗v1∗ln(cosh((v – v0)/v1));
I(p, n) <+ ddt(q);
end
endmodule

You can modify this model to add a series resistance as follows:

Code:

module varactor(p, n);
inout p, n;
electrical p, n, int;
parameter real c0 = 1p from (0:inf); // nominal capacitance (F)
parameter real c1 = 0.5p from [0:c0); // maximum capacitance change from nominal (F)
parameter real v0 = 0; // voltage for nominal capacitance (V)
parameter real v1 = 1 from (0:inf); // voltage change for maximum capacitance (V)
parameter real r = 0 from [0:inf); // series resistance (Ohms)
branch (p, int) res;
branch (int, n) cap;
real q, v;
analog begin
v = V(cap);
q = c0∗v + c1∗v1∗ln(cosh((v – v0)/v1));
I(cap) <+ ddt(q);
V(res) <+ r * I(res);
end
endmodule

Alternatively, you use an implicit formulation:

Code:

module varactor(p, n);
inout p, n;
electrical p, n, int;
parameter real c0 = 1p from (0:inf); // nominal capacitance (F)
parameter real c1 = 0.5p from [0:c0); // maximum capacitance change from nominal (F)
parameter real v0 = 0; // voltage for nominal capacitance (V)
parameter real v1 = 1 from (0:inf); // voltage change for maximum capacitance (V)
parameter real r = 0 from [0:inf); // series resistance (Ohms)
real q, v;
analog begin
v = V(p,n) - r*I(p,n)
q = c0∗v + c1∗v1∗ln(cosh((v – v0)/v1));
I(p, n) <+ ddt(q);
end
endmodule

-Ken

Title: Re: Is there a way to implement this kind of RC model in veriloga?
Post by ray0923 on Jan 9^th, 2018, 2:34pm

Is that the same if i replace i(res) with i(cap)?

Title: Re: Is there a way to implement this kind of RC model in veriloga?
Post by Ken Kundert on Jan 9^th, 2018, 3:41pm

More words are required.

Title: Re: Is there a way to implement this kind of RC model in veriloga?
Post by Geoffrey_Coram on Jan 10^th, 2018, 6:22am

I think the question is whether one can replace "I(res)" in the second line:

Code:

I(cap) <+ ddt(q);
V(res) <+ r * I(res);

by "I(cap)".

While I(cap) and I(res) are equal by KCL, the matrix stamps (what the simulator sees when trying to solve the circuit) are different. Maybe it reduces to the same thing, but why would you want to do this?