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Design Languages >> Verilog-AMS >> How to Write a PWL Current Source,Please Help!!!THX
https://designers-guide.org/forum/YaBB.pl?num=1510206643

Message started by DavidAnger on Nov 8^th, 2017, 9:50pm

Title: How to Write a PWL Current Source,Please Help!!!THX
Post by DavidAnger on Nov 8^th, 2017, 9:50pm

Hello!
I want to make a MTK PE+ protocol tester.
So I want make a current wave like this:
_|-|_|-|_|---|_|---|_|---|_|-----|_
(i_bus=0->delay TimeD->i_bus=itarget->delay TimeC->i_bus=0->delay TimeD->i_bus=itarget->delay TimeC->i_bus=0->delay TimeD->i_bus=itarget->delay TimeB->i_bus=0->delay TimeD->i_bus=itarget->delay TimeB->i_bus=0->delay TimeD->i_bus=itarget->delay TimeB->i_bus=0->delay TimeD->i_bus=itarget->delay TimeA->i_bus=0->delay TimeD)

*TimeA=500ms *TimeB=300ms *TimeC=TimeD=100ms

my code is:

Code:

case(mod)
...
3: begin
if ( V(vtarget) < 2 ) begin //Reset
next1 = $abstime + TimeWDT;
@(timer($abstime , next1)) i_bus = 0;
end
else if ( V(vbus) < ( V(vtarget) - 1 ) ) begin //this part is current wave
repeat( 2 ) begin
i_bus = 0;
next1 = $abstime + TimeD;
next2 = next1 + TimeC;
@(timer(next1 , next2)) i_bus = V(itarget);
end
repeat( 3 ) begin
next1 = $abstime + TimeD;
@(timer($abstime , next1)) i_bus = 0;
next2 = $abstime + TimeB;
@(timer($abstime , next2)) i_bus = V(itarget);
end
next1 = $abstime + TimeD;
@(timer($abstime , next1)) i_bus = 0;
next2 = $abstime + TimeA;
end
else if ( V(vbus) > ( V(vtarget) + 1 ) )begin //this part is another current wave
repeat( 3 ) begin
next1 = $abstime + TimeD;
@(timer($abstime , next1)) i_bus = 0;
next2 = $abstime + TimeB;
@(timer($abstime , next2)) i_bus = V(itarget);
end
repeat( 2 ) begin
next1 = $abstime + TimeD;
@(timer($abstime , next1)) i_bus = 0;
next2 = $abstime + TimeC;
@(timer($abstime , next2)) i_bus = V(itarget);
end
next1 = $abstime + TimeD;
@(timer($abstime , next1)) i_bus = 0;
next2 = $abstime + TimeA;
@(timer($abstime , next2)) i_bus = V(itarget);
end
end
...

I know it is not right, but i don't know how to make delay in the loop.

Please help, Thanks!

Title: Re: How to Write a PWL Current Source,Please Help!!!THX
Post by Geoffrey_Coram on Nov 9^th, 2017, 7:05am

I can't figure out what you are trying to do. I don't understand this:
i_bus=0->delay TimeD->i_bus=itarget->delay TimeC->i_bus=0...

and I don't know what MTK PE+ is.

To me, a "PWL current source" is a spice element that takes an array of time,value pairs and generates a current that depends only on the time ($abstime). Your code shows that there is some additional input based on V(vbus) and V(vtarget), but I don't know what that is, or how it relates to the current wave you mention in the text.

Title: Re: How to Write a PWL Current Source,Please Help!!!THX
Post by DavidAnger on Nov 9^th, 2017, 10:54pm

Geoffrey_Coram wrote on Nov 9^th, 2017, 7:05am:

Hi, Geoffrey_Coram

I just want to known how to make delay in a loop.
Can I make a PWL source with Duty 30% like this?

Code:

module PWL(out);
voltage out;

parameter real Period = 100u;
parameter real Duty = 30;

real pulse_timer;
real lpulse_timer;
real v_out;
analog begin
pulse_timer = $abstime + Period*Duty/100;
while($abstime < pulse_timer)
v_out = 1;
lpulse_timer = $abstimer + Period*(100-Duty)/100;
while($abstime < lpulse_timer)
v_out = 0;
end

analog V(out) <+ v_out;

endmodule

I use this model to running, the simulation will get stuck at the "while" loop.

So how to solved this?

Title: Re: How to Write a PWL Current Source,Please Help!!!THX
Post by Geoffrey_Coram on Nov 10^th, 2017, 7:29am

Code:

pulse_timer = $abstime + Period*Duty/100;
while($abstime < pulse_timer)
v_out = 1;

So, at the start of the simulation, $abstime = 0, and then pulse_timer = 0 + 100u*30/100, and of course the while loop gets stuck: $abstime =0 is less than 30u, so it keeps looping.

Title: Re: How to Write a PWL Current Source,Please Help!!!THX
Post by Geoffrey_Coram on Nov 10^th, 2017, 7:39am

Try this:

Code:

module PWL(out);
output out;
voltage out;

parameter real Period = 100u;
parameter real Duty = 30;

real t_modulo_period;
real v_out;
analog begin
t_modulo_period = $abstime;
while (t_modulo_period > Period)
t_modulo_period = t_modulo_period - Period;
if (t_modulo_period < Period * Duty/100)
v_out = 1;
else
v_out = 0;

V(out) <+ v_out;
bound_step(0.1*Period);
end
endmodule

Title: Re: How to Write a PWL Current Source,Please Help!!!THX
Post by DavidAnger on Nov 12^th, 2017, 7:04pm

Geoffrey_Coram wrote on Nov 10^th, 2017, 7:29am:

Code:

pulse_timer = $abstime + Period*Duty/100;
while($abstime < pulse_timer)
v_out = 1;

So, at the start of the simulation, $abstime = 0, and then pulse_timer = 0 + 100u*30/100, and of course the while loop gets stuck: $abstime =0 is less than 30u, so it keeps looping.

Thanks a lot!
OK I got It. It's different between software that the expressions are not spend time. :D

So $abstime just can changed at the analog loop beginning?
And how can I make delay in "analog" loop? just like verilog "#delay"?

Title: Re: How to Write a PWL Current Source,Please Help!!!THX
Post by Geoffrey_Coram on Nov 13^th, 2017, 6:22am

There is no analog equivalent to digital #delay.

You can do something like

Code:

t_after_delay = $abstime - Delay;
if( t_after_delay >= 0) begin
t_modulo_period = t_after_delay;
...

Title: Re: How to Write a PWL Current Source,Please Help!!!THX
Post by DavidAnger on Nov 13^th, 2017, 10:57pm

Geoffrey_Coram wrote on Nov 13^th, 2017, 6:22am:

There is no analog equivalent to digital #delay.

You can do something like

Code:

t_after_delay = $abstime - Delay;
if( t_after_delay >= 0) begin
t_modulo_period = t_after_delay;
...

Great Thanks! :D