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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Port declaration in ADC model https://designers-guide.org/forum/YaBB.pl?num=1505907902 Message started by samiran on Sep 20th, 2017, 4:45am |
Title: Port declaration in ADC model Post by samiran on Sep 20th, 2017, 4:45am Hi, I am trying to use the ADC Verilog-A model given in the "Designer's Guide of Verilog AMS" book (Ch. 3, Listing 26). The code is - Code:
In this the output port has variable width defined by the integer variable "bits". The problem that I am facing is - when I am trying to create the symbol (Cadence Virtuoso 6.1.6), it is taking the output port name as out<0:-1>. Changing it to out is not accepted. However, if I set bits = 8, and hard-code the port declaration as - Code:
then there is no issue - the port name is taken as out<0:7>. Can somebody, please help me out in fixing this problem (how to properly set the output port name even after keeping port word-length variable through the parameter bits. |
Title: Re: Port declaration in ADC model Post by Ken Kundert on Sep 20th, 2017, 9:15am ADE does not support parameterized bus widths. You must eliminate the bits parameter and make the number of bits a constant. -Ken |
Title: Re: Port declaration in ADC model Post by samiran on Sep 20th, 2017, 8:34pm Thanks for the reply, Ken. Can the ams simulator handle parameterized bus width? |
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