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Simulators >> Circuit Simulators >> Analog Assertion using PSL (Property Specific Language )
https://designers-guide.org/forum/YaBB.pl?num=1502282249

Message started by Gp on Aug 9^th, 2017, 5:37am

Title: Analog Assertion using PSL (Property Specific Language )
Post by Gp on Aug 9^th, 2017, 5:37am

Hi,

I have implemented the PSL checkers for Vdd range (0.75 to 1.6). Exceed this range checkers should fail.
Now my query is, when I integrate the (.psl) file in file list(.fl) file then (.psl) file did not compile and simulate. I think I am facing the psl file setup issue. my psl checker is following:

module ams_assert_check();
inout vdd;
electrical vdd;
psl property P1={V(vdd)>0.75;V(vdd)<1.6} @cross(V(vdd)-0.75));
psl assert P1;
endmodule

So, From this anything file or method are missing? and how can I bind the PSL assertion?

I am including the psl file with irun command. So, how can I include through irun command or .fl (filelist) file?

So, Kindly resolve my query.

Title: Re: Analog Assertion using PSL (Property Specific Language )
Post by Andrew Beckett on Aug 9^th, 2017, 11:26pm

Several things wrong here:

You've omitted the I/O list of the module
psl assertions should be inside comments
the syntax of the psl assertion is incorrect - it's not clear what you're trying to do so correcting it is not that easy
you didn't say how you were incorporating these assertions (you refer to .fl and .psl which are presumably your naming convention)
Did you run with -assert on the irun command line?

Even if I change the code as follows:

Code:

`include "disciplines.vams"

module ams_assert_check(vdd);
inout vdd;
electrical vdd;
//psl property P1={V(vdd)>0.75;V(vdd)<1.6} @cross(V(vdd)-0.75));
//psl assert P1;
endmodule

module top;

and I run with -assert (and have instantiated ams_assert_check in my design), it fails with an error because the PSL syntax is incorrect.

Have you read the section on PSL assertions in the AMS Designer User Guide (search in cdnshelp for "AMS psl" and you should find it)?

Regards,

Andrew.

Title: Re: Analog Assertion using PSL (Property Specific Language )
Post by Gp on Aug 28^th, 2017, 1:42am

Hi,

I have design and testbench both are in Verilog-ams As shown in below. And tried with -assert option. it is working fine now.

Now I want to try the following example with design in Verilog-AMS and test bench in System Verilog. So, is it Possible? How?
And How to bind this example with VUNIT?

//************************ Design (test.vams) *************************//
`timescale 1ns/1ps
`include "disciplines.vams"

module test (in,out);
inout in,out;
electrical in,out;

analog begin
V(out) <+ 3.0 + V(in);
end

//psl out_check: assert always ({V(out)> 5.0}) @(cross (V(in)-0.5));

endmodule
*********************************************************

//********************** Testbench (test_tb.vams) *****************

module test_tb (in_tb,out_tb);
inout in_tb,out_tb;
electrical in_tb,out_tb;

// analog begin
// V(in_tb)<+ 1.0;
// end
vsource #(.type("pwl"), .wave({"0","0","5n","0","6n","1","9n","1","10n","0"})) V0 ( in_tb , cds_globals.\gnd! );

test dut (.in (in_tb),
.out (out_tb));

endmodule

//**********************************************************************

Title: Re: Analog Assertion using PSL (Property Specific Language )
Post by Andrew Beckett on Sep 9^th, 2017, 12:16am

Not really enough information to go on here. To simulate Verilog-AMS and SystemVerilog together just provide both files to irun - not much you have to do. For the rest of it, it's not clear what you're doing or quite what you're asking, I'm afraid.

Andrew.

Title: Re: Analog Assertion using PSL (Property Specific Language )
Post by Gp on Sep 11^th, 2017, 1:39am

In Verilog-ams DUT, I have defined electrical ports and In Verilog-ams test bench also defined electrical ports. In this case, No connect module inserted.
Now in Verilog-AMS DUT and SV test bench, connect module (E2R or E2L) inserted.
But I want to connect Verilog-AMS and SV test bench without any insert connect module. I mean, in SV test bench is it possible to define ports in electrical discipline? (Direct way is not possible but in any way).
My final aim is no connect module insert between Verilog-AMS and SV testbench.

Title: Re: Analog Assertion using PSL (Property Specific Language )
Post by Andrew Beckett on Sep 11^th, 2017, 3:39am

No, this is not (yet) possible. You'd need SystemVerilog-AMS which is not yet a standard (work in progress).

However, if the discipline is not defined at the SystemVerilog level (i.e. only in the lower level Verilog-AMS modules) then it would work - there would be no need for any connect modules to be inserted as discipline resolution should propagate the discipline from the lower level cells to the top level.

Andrew