The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> settling time of charge pump in a CPPLL.
https://designers-guide.org/forum/YaBB.pl?num=1500301826

Message started by Jacki on Jul 17^th, 2017, 7:30am

Title: settling time of charge pump in a CPPLL.
Post by Jacki on Jul 17^th, 2017, 7:30am

Hello,

Currently I am simulating a charge pump used in a CPPLL. I try to understand the dead zone of CP, and find the minimum delay in the PFD. From my understand, the dead zone can be considerd when the current in either UP or DOWN current source from 0 settled to the stable current as shown in the figure below.
Am I right to understand the dead zone in this way, and design the delay in PFD using the "settling time" of the current in the charge pump?

Title: Re: settling time of charge pump in a CPPLL.
Post by Jacki on Jul 17^th, 2017, 7:31am

the simulated current (DOWN) in the charge pump, and I mark the "settling time" I used to determine the delay time.

Title: Re: settling time of charge pump in a CPPLL.
Post by Jacki on Jul 17^th, 2017, 7:37am

By the way, i find the single transistor as the current source in the charge pump gives the fastest response (settling time). The cascode transistor as the current source in the charge pump will have slower settling time. I wonder how people design the charge pump for an accurate high-speed PLL? If an opamp is used to reduce the current mismatch, how fast the opamp shall be (bandwidth)?
I am new in PLL, maybe some questions are very simple even wrong, I am grateful to your answers.
Thank you.

Title: Re: settling time of charge pump in a CPPLL.
Post by Berti-2 on Jul 17^th, 2017, 11:34pm

Hi Jacki,

I would assume that the delay in the PFD just needs to be long enough, so that you always get a current pulse from the charge-pump (over PVT). Your "settling simulation" therefore seems like a reasonable criteria even though more on the pessimistic side from my point of view.

The cascode devices should improve settling as they keep VDS constant of the larger current mirror devices, and shield the large parasitic cap from the output.

Regards

Title: Re: settling time of charge pump in a CPPLL.
Post by Jacki on Jul 18^th, 2017, 4:27am

Hi Berti-2,

Thank you very much for your reply, I think I get some points. I just wonder the power consumption will be higher if the delay is too long, so I try to find the optimum delay in the PFD. Also if there is current mismatch, the more delay time we have, I am afraid the more static phase error we will have in the PFD and CP.

Title: Re: settling time of charge pump in a CPPLL.
Post by Jacki on Jul 18^th, 2017, 4:51am

By the way, regarding the discussion that cascode current source in the charge pump has smaller settling time than the single transistor current source, I can't follow it. In my simulation, it is clear cascode current source has slower response than the single transistor current source, and I think it makes sense because instead of settling one transistor, in cascode current source two transistors need to be settled into saturation region.
One more question, how to make the settling time of the current source (from 0 to a precise current value) in the charge pump as fast as possible?

Title: Re: settling time of charge pump in a CPPLL.
Post by Berti-2 on Jul 18^th, 2017, 11:12pm

Regarding the length of the reset pulses, I wouldn't be worried about current consumption, but more about additional noise you get from the charge-pump.

In order to get fast settling time, the current in the charge-pump is typically never turned off, but steered between the output and a dummy branch (that's why the reset pulse length should not impact much the current consumption). If you are just steering the current, the cascode should improve settling.

Title: Re: settling time of charge pump in a CPPLL.
Post by Jacki on Jul 18^th, 2017, 11:42pm

Got it. Thank you very much. I do see some charge pumps have switched branches.

Title: Re: settling time of charge pump in a CPPLL.
Post by Hercules Poirot on Aug 8^th, 2017, 5:15am

Adding to Berti-2's reply, see the attached image. I have done this a couple of times.