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Simulators >> Logic Simulators >> Validation of $write() for encrypted Verilog-A modules in Cadence Tool
https://designers-guide.org/forum/YaBB.pl?num=1497886804

Message started by cheap_salary on Jun 19^th, 2017, 8:40am

Title: Validation of $write() for encrypted Verilog-A modules in Cadence Tool
Post by cheap_salary on Jun 19^th, 2017, 8:40am

I can encrypt the "mymodule.va" file in both Cadence Tool and Synopsys HSPICE.

For Cadence Tool

Code:

unix> ncprotect -extension vap -language vlog -autoprotect mymodule.va

For Synopsys HSPICE

Code:

unix> metaencrypt -i mymodule.va -o mymodule.vap -t randkey

My Verilog-A module includes $write().

Code:

analog begin
@(initial_step) begin
$write("\n");
case(mode)
0 : $write("%M: Constant Current Mode(Inom=%.2fuA)\n", Inom/1u);

1 : $write("%M: Constant Resistance Mode(Vnom=%gVolts, Inom=%.2fuA, Rnom=%.2fkohm)\n",
Vnom, Inom/1u, Rnom/1k);

2 : $write("%M: Clip Current Mode(Imin=%.2fuA, Imax=%.2fuA, Vth=%gVolts, Vknee=%gVolts)\n",
Imin/1u, Imax/1u, Vth, Vknee);

In HSPICE, $write() is valid even for encrypted Verilog-A modules.

However $write() is not valid for encrypted Verilog-A modules in Cadence Tools.

How can I make $write() valid in Cadence Tool ?

Title: Re: Validation of $write() for encrypted Verilog-A modules in Cadence Tool
Post by Andrew Beckett on Jul 25^th, 2017, 9:38am

The only way is to use the //pragma constructs in the file to turn on and off encryption so that the $write statements are not encrypted.

Maybe you should file an enhancement CCR to allow ncprotect to have an option to allow $write statements to work when inside encrypted code. It would have to be an encryption-time decision, I think.

I've not found any other requests for this - but it seems a reasonable request to me that you should be allowed to decide whether they are enabled or not.

Regards,

Andrew.

Title: Re: Validation of $write() for encrypted Verilog-A modules in Cadence Tool
Post by cheap_salary on Jul 28^th, 2017, 12:45am

Thank for answering.

Code:

Warning from spectre during AHDL read-in.
WARNING (VACOMP-2343): Cannot display/strobe/write information or call $system from a protected analog block.

Andrew Beckett wrote on Jul 25^th, 2017, 9:38am:

The only way is to use the //pragma constructs in the file to turn on and off encryption
so that the $write statements are not encrypted.

Could you teach me what I should do in detail ?

Do you mean like following ?

Code:

`pragma protect begin
module A; //This module will be encrypted
...
endmodule
`pragma protect end

module B; //This module will not be encrypted
...
endmodule

Title: Re: Validation of $write() for encrypted Verilog-A modules in Cadence Tool
Post by Andrew Beckett on Aug 2^nd, 2017, 9:14pm

Here's an example I used:

Code:

`include "disciplines.vams"

//pragma protect
//pragma protect begin
module desguide2 (mon,vss);
inout mon,vss;
electrical mon,vss;

parameter real Inom=2u;
parameter real Vnom=2.0;
parameter real Rnom=1k;
parameter real Vknee=3.0;
parameter real Vth=0.7;
parameter real Imin=0.1u;
parameter real Imax=10u;
parameter integer mode=1;

analog begin
@(initial_step) begin
//pragma protect end
$write("\n");
case(mode)
0 : $write("%M: Constant Current Mode(Inom=%.2fuA)\n", Inom/1u);

1 : $write("%M: Constant Resistance Mode(Vnom=%gVolts, Inom=%.2fuA, Rnom=%.2fkohm)\n",
Vnom, Inom/1u, Rnom/1k);

2 : $write("%M: Clip Current Mode(Imin=%.2fuA, Imax=%.2fuA, Vth=%gVolts, Vknee=%gVolts)\n",
Imin/1u, Imax/1u, Vth, Vknee);
endcase
//pragma protect
//pragma protect begin
end

end

endmodule
//pragma protect end

Regards,

Andrew.