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Modeling >> Behavioral Models >> Verilog-A, one time event
https://designers-guide.org/forum/YaBB.pl?num=1496689813

Message started by balshoy on Jun 5^th, 2017, 12:10pm

Title: Verilog-A, one time event
Post by balshoy on Jun 5^th, 2017, 12:10pm

Hi,

I am developing a verilog-A model for a device. I want to write a function that is executed only one time in the simulation during the device first transition from high resistive state to a low resistive state. I looked at analog events but did not find a function that provides this functionality I want. I tried to do it using an if..else statement but it gave me convergence error.

Can someone help me with that?

Thanks
- See more at: https://community.cadence.com/cadence_technology_forums/f/38/t/37392#sthash.1mJCXNnn.dpuf

Title: Re: Verilog-A, one time event
Post by Ken Kundert on Jun 5^th, 2017, 12:48pm

Try the timer event.

-Ken