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Design >> Analog Design >> Common Source Amplifier with Current Mirror Load Design using gm/Id method
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Message started by Bean Nakamura on Apr 1^st, 2017, 4:08am

Title: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by Bean Nakamura on Apr 1^st, 2017, 4:08am

Hello all,
I have a question on designing using gm/Id. So I've successfully designed a CS Amp with resistive and PMOS active load and now I'm currently trying to design CS Amp with Current Mirror Load in 130nm using gm/Id technique. Shout out to ULPAnalog for introducing me to this technique! :)
Although this technique worked perfectly when designing with resistive and pmos load, the gain and output voltage was not as expected when using current mirror load. I suspect it has something to do with the output voltage or the DC operating point.

Here's what I've done:-

1)Characterized NMOS with Vdrain =0.6V, Vsource =0V , Vgate is swept from 0 to 1.2V.
The gm/Id, Id/W and gm/gds is plotted with respect to Vgs.

2)Characterized PMOS with Vdrain = 0.6V, Vsource =1.2V , Vgate is swept from 0 to 1.2V.
The gm/Id, Id/W and gm/gds is plotted with respect to Vgs.

3)Gain equation of this architecture is given by (gm of nmos)/gds,nmos+gds,pmos

4)Chose gm to be 3.14mS, assuming the desired BW is 100MHz with load capacitance of 5pF. (I didn't simulate with the cap since my focus is the gain rather than BW don't think this matters tho).

4)DEvice dimensions
NMOS = 99um/1.5um PMOS = 60um/1um Current = 278uA.

5)Calculated gain should be around 277V/V but the simulated gain was around 2V/V.

6)As far as the The DC operating point of the transistors, only the DC current matches the calculation. The gm of devices as well as drain voltages of the device do not match/not as expected.

7)NMOS was biased at 450mV.

9)I have attached the schematic as well as the transistor characterization plots, if it helps.

Questions:-

1)What did I do wrong or what can I change? I can't for the life of me figure it out. I did do a DC analysis using the sizing mentioned above and at the point I biased my NMOS I should have gotten close to 0.6V instead of 0.996V which is causing my PMOS to be in linear instead of saturation region.

2)Is it normal for it to have a large size? What is the typical sizing of an op amp? Does the PMOS or NMOS reach more than 100um in any case? I'm used to designing digital standard cells (which are relatively smaller) and the large size of the op amp transistor is scaring me a bit to the point where I have doubts about my design lol.

3)I suspect there is a tradeoff here between output voltage/swing and gain but I can't quite figure it out. I characterized my transistors such that the output voltage would be half of the Vdd (1.2V) for higher voltage swing. Should I re-characterize my transistors?

Any and all help is greatly appreciated and thanks in advance! :) :)
Edit: This thing won't let me attach multiple pics, will post the plots later.

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by Bean Nakamura on Apr 1^st, 2017, 8:06am

gm/gds for NMOS

gm/Id for NMOS

Id/W for NMOS

gm/gds for PMOS

gm/Id for PMOS

Id/W for PMOS

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by ULPAnalog on Apr 1^st, 2017, 10:44pm

Hi

I believe you are on the right track overall. The problem with active load is that you are now in a situation with two current sources connected to each other and trying to fix the operating point. Even the slightest mismatch between the currents can knock the amplifier out of its nominal operating point. This is the reason why open loop amplifiers are extremely difficult to work with.

As with most such problems, negative feedback comes to rescue. If you can set up DC negative feedback around your amplifier, you shall see it getting biased correctly as you would expect. Just to test it out, you may try adding a resistive feedback between the output of CS stage to its input and see it getting biased correctly at DC.

It's not uncommon to have 100u length transistors. In fact for me they are small!! I work with biosignal amps and flicker noise requirements at such low frequencies, in the absence of chopping forces me to use transistors whose dimensions sometimes exceed 1000u. You could literally see them.

To reiterate, I believe you are in the right track overall and enjoy designing the amps.

Best regards

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by Bean Nakamura on Apr 2^nd, 2017, 5:00am

Thank you so much ULPAnalog! You are truly a godsent! It worked! I got the DC operating point to be where I wanted it to. I don't really know how DC negative feedback works in principle or mathematically but I guess I'll try to figure that out on my own. I have found some materials on the topic. If you have any materials that you personally have read/used in the past I'd appreciate it if you could point me to that direction.

Also, on a sidenote, if you don't mind me asking, did you learn all this as you go or did they teach this in school? Not that I'm not paying attention in class or anything, it's just that theoretical stuff and hands on are totally different (I'm still a student by the way). I did pick up bits and pieces of information from online pdf lectures like UCLA, Berkeley, Stanford etc. I was kinda hoping the industry would have a 1-2 week tutorial/ hands-on on this kind of stuff which I think would help a lot when students enter the workforce. Anyway, thanks again!! You were a lot of help! :) :)

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by ULPAnalog on Apr 2^nd, 2017, 12:10pm

On the DC negative feedback, I learnt about it during my masters, when I actually came across fully differential amplifiers. Till that point, I never really wondered on how the DC biases are set for a single ended opamp honestly. During my PhD, given that I worked in biosignal readouts, AC coupling and hence DC negative feedback became part and parcel of the instrumentation amplifiers I designed, refining my understanding of the subject. There is still a long way to go though.

Most of the things are self taught. I like to think of analog IC design as an art. Art, in general, one can teach basic principles but one can only gain mastery by practice. To me analog IC design is no different. I never really worked in "real" industry doing IC design. I work out of research labs and here there is certainly no getting started with analog IC design kind of tutorial. There are tutorials and training on how to use tools, for example cadence design suite but not on how to design circuits.

Perhaps someone from industry background can shed some light on how junior engineers are brought up to speed in IC design.

BTW, this particular reply is not design related, so I am not sure if it is appropriate to post it here.

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by DanielLam on Apr 2^nd, 2017, 11:14pm

Hi, I might be able to shed some light on junior IC designers. I have a bs+masters in EE (modeled, designed, laid out, tested a SAR ADC for my thesis). I've been in industry a little under 2 years.

"Also, on a sidenote, if you don't mind me asking, did you learn all this as you go or did they teach this in school?"

Both. But you should learn and try as much as you can in school. The same questions I had in school are the same problems I face in industry. So if you answer a lot of your questions while in school, you will be MUCH MUCH better in industry or anywhere. Also, while in school, you can basically ask the professor as many questions as you want. In industry, you might have to be a little selective in order to not seem like a burden.

"Perhaps someone from industry background can shed some light on how junior engineers are brought up to speed in IC design."

You need to really want to get things to work, and understand why they work, and the limitations. If your fundamentals are solid, you will go very very far. For example, I'm dealing with two-stage opamp gain, speed, noise, swing issues at the moment.

I keep up with papers on IEEE, and I also review class notes from Stanford, TAMU, Berkeley, and wherever I find good notes. The videos on SCSS society are very informative as well. I've read 75% of the Razavi CMOS book, and plan on reading more and re-reading (and doing problems).

"It's not uncommon to have 100u length transistors. In fact for me they are small!!"

All right, this comment made me chuckle. I had to re-read that you said length, and not width. At that point, would you rather try a chopping scheme for flicker? I usually work with <1 um length transistors.

Regards,
Daniel Lam

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by Bean Nakamura on Apr 3^rd, 2017, 12:23am

Thanks for your insights Daniel! It's always good to have someone from the industry to talk with about these kind of things. I will definitely follow in your foot steps and cover the Behzad Razavi book page by page as well as watch SCSS videos.

Thanks again! :) :)

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by ULPAnalog on Apr 3^rd, 2017, 12:48am

Thanks Daniel for your insights.

Quote:

"It's not uncommon to have 100u length transistors. In fact for me they are small!!"

All right, this comment made me chuckle. I had to re-read that you said length, and not width. At that point, would you rather try a chopping scheme for flicker? I usually work with <1 um length transistors.

Ok, a little bit of correction and clarification. Indeed 100u length devices are not uncommon but the 1000u device I mentioned was actually width (I said dimension, not length per se in my defense, not that it matters anyway).

The problem is that at times we work at nA current levels and to kill (minimize) the noise contribution of the active load, we are forced to bias the active load in strong inversion saturation (also good for current source matching). nA current levels, strong inversion saturation would mean long length devices (yes they exceed 100u) with weird aspect ratios.

Chopping is great, but depending on where we chop we might either have to compromise the CMRR or input impedance and maximum DC handling capabilities. There are many ways to handle those, published by several groups, including ours.

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by Bean Nakamura on Apr 3^rd, 2017, 10:16am

Hello again!
Just to keep this thread going, I was just wondering if the difficulty in stabilizing the DC operating point also occurs in standard textbook differential amplifier designs with current mirror load and current mirror biasing. I haven't tried this out yet but plan to do so shortly.
You mentioned earlier that because the operating point is being fixed by two current sources, DC operating point stabilization is hard to achieve.
I would imagine this would also occur in the differential amplifier. If so, would connecting a resistor the same way as you suggested in the CS amplifier fix the problem? Or is there a more practical way of doing it that's not mentioned it literature?

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by AnilReddy on Apr 3^rd, 2017, 11:18pm

Bean,

Any high-impedance node would have similar issues. All high-impedance nodes within amps need to be stabilized by some means, ex. neg. feedback.

thanks.

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by ULPAnalog on Apr 4^th, 2017, 1:15am

A classic differential amplifier will have the problem that you encountered in CS amplifier. If you can live with lower gain, you may go for current mirror OTA with no output stage and its gain will be at best 2-5 V/V in practice.

Usually, amps are used in negative feedback systems. Unless the feedback is purely capacitive or an inductor at the input in inverting config, you will have some sort of DC negative feedback. For example as resistive gain amplifier has DC negative feedback.

Bioamps, that are capacitively coupled usually have a extremely large feedback resistance realized through pseudo resistors (very difficult to control and susceptible to PVT. Good for academic publications only). More recently switched capacitor and switched resistor feedback are getting popular for stabilizing DC operating point.

In open loop amplifier applications, the high imepdance nodes are typically charged to appropriate DC levels before the start of amplification phase. Bottom line is, if the amplifier is not properly biased at DC or before it begins to amplify the signal, it does not work as an amplifier with designed spec any more.

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by Bean Nakamura on Apr 4^th, 2017, 5:03am

AnilReddy,
Thanks for your input! I actually tried using negative feedback on my CS Amplifier and although it stabilized the operating point the gain actually decreases. I already worked out the small-signal analysis and found out the reason why. My only question is there a way to mitigate the drop in gain induced by the negative feedback? Also, without the negative feedback, I get a higher gain but with lower voltage swing. Would I be correct in saying this whole thing has to have a tradeoff between voltage swing and gain?

Thanks!

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by Bean Nakamura on Apr 4^th, 2017, 5:14am

Thanks for your insights ULPAnalog! Definitely learned a lot here. Especially interested in those bioamps. I will definitely look into switched capacitor, switched resistor feedback circuits and the part about precharging the high impedance nodes. These are some really advanced stuff you mentioned here, it's always good to learn these kinds of things! Thanks again!

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by ocmob on Apr 5^th, 2017, 12:55am

Bean as for the feedback questions - you will find your answer in Razavi textbook, there is a whole chapter dedicated to feedback and it is a good idea to read it thoroughly. It is important to have a good understanding of feedback.

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by Bean Nakamura on Apr 5^th, 2017, 7:14pm

Thanks ocmb! Will get a copy of Behzad Razavi's book right away!

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by Bean Nakamura on Apr 30^th, 2017, 5:03am

Hello again!

I decided to continue here instead of making a new thread since what I'm about to ask is closely related to this post.

So, I have a question regarding the frequency response of CS/Diff/2-stage op amps and I hope you don't mind answering them. I have designed the amps using the gm/Id method and have met the target for the gain specs. However, I neglected to take into account the bandwidth (BW), slew rate (SR) and phase margin (PM) when designing them. Initially, I only wanted to familiarize myself with the gm/Id technique so my main focus was gain. Now I'm wondering how to design the amps taking into consideration the said specs.

Questions:-
1)How do I go about designing the amps while also taking into account the BW,SR and PM while getting the same amount of gain? Using the gm/ID method. I looked it up online and some have suggested to plot Cgs and fT when characterizing the transistor. How does this come into play?

2)I saw some formula for the transfer function of the amps posted online. In this formula, Cdb, Cgs and Cgd are also included. Would I have to plot this as well?

3)Is there an easy/intuitive way to design according to the specs for BW, SR and PM? The formula posted online looks really intimidating. I have watched several videos on the derivation and so I am familiar of the process. However, I do wish there was an easier way to do this, if possible. How is this (designing for BW, SR, PM) done in the IC design industry?

4)I will be using the designed op-amp to make a simple 3-bit ADC, is there a rule of thumb on what gain and BW I should shoot for?

Thanks in advance!

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by ULPAnalog on May 1^st, 2017, 11:30am

Bean

I would recommend you to have a look at the paper titled "A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on- insulator micropower OTA". This deals with the questions on SR and BW and to some extent PM while designing a two stage amplifier (although the amplifier presented in the above paper is a single dominant pole one, even without compensation). You may find it helpful.

You will notice that the dominant pole and hence the GBW of the two stage Miller compensated OTA is determined by the Miller cap and the gain of second stage and the transcondutance of the first stage among others. Also the SR is determined by the DC bias current of the first stage and Miller cap (to a large extent). I would recommend you to have a look at two stage op-amp design procedure outlined in Allen and Holberg book/lecture notes to get an idea about where to start.

If your settling error needs to be less than, say 0.1LSB (arbitrary), then your steady state error needs to be less than 0.1LSB, which sets the min DC gain. Depending on the sampling frequency and the shape of sampling clock, you would want to have a BW sufficient enough to ensure that you settle down to 0.1LSB in the track phase.

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by Bean Nakamura on May 1^st, 2017, 9:19pm

Thanks again ULPAnalog!
I will definitely get a hold of the materials you mentioned.

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by Roy on May 18^th, 2017, 8:09pm

Bean Nakamura wrote on Apr 3^rd, 2017, 12:23am:

Hi, Bean Nakamura. I'm a freshman for IC design.
If you don't mind, I want to know what is the full name of the SCSS, and where can I get their video. Thanks.

Title: Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Post by Bean Nakamura on May 18^th, 2017, 10:11pm

Hello Roy. SSCS stands for IEEE's Solid State Circuit Society which talks about IC Design and probably some other stuff. You should be able to google their videos/tutorials online. Good luck! :)