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Design >> Analog Design >> Why should CP - PLL have limited bandwidth?
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Message started by subtr on Jan 8^th, 2017, 10:51pm

Title: Why should CP - PLL have limited bandwidth?
Post by subtr on Jan 8^th, 2017, 10:51pm

There are reasons why PLL has to have low bandwidth in comparison to Fref. I'm currently talking about a simple charge pump based PLL. One reason I know is the reference spur should be minimize because it will cause VCO to change its frequency which will again propagate through the loop. The bandwidth cannot be increased much because of the stability issue. There is a thumb rule followed by people to make the bandwidth Fref/10. My question is : Which is more fundamental reason for this thumb rule? Is it the reference spur or the stability? I realize that our s-domain wouldn't work if our bandwidth is comparable to the Fref. It's hard to decouple these because averaging and removing reference spur, by using some golden PD automatically means I'm doing a low pass in frequency domain. But it would be great if someone could explain it in simple words.

Title: Re: Why should CP - PLL have limited bandwidth?
Post by loose-electron on Mar 20^th, 2017, 9:24pm

you don't want the loop to respond to the reference frequency on every clock edge is the primary reason. The PLL should respond to the cumulative results of multiple phase errors.

Title: Re: Why should CP - PLL have limited bandwidth?
Post by BillH on May 30^th, 2017, 1:32pm

Depending on what specs you are trying to meet the loop bandwidth is either set to insure stability, minimize reference spurs, minimize integrated phase noise, or minimize contribution of Delta-Sigma Modulation noise.

In my experience, mostly working on PLL's in communication systems, the loop bandwidth is usually set to optimize integrated phase noise. This bandwidth usually tends to be close the offset frequency for which the contribution from the PLL noise sources (ref, PFD, CP, divider, loop filter) which tend to be flat wrt offset frequency is equal to the VCO noise contribution (which tends to be dropping 20dB/dec wrt offset frequency).

Title: Re: Why should CP - PLL have limited bandwidth?
Post by BillH on May 30^th, 2017, 1:38pm

The fundamental reason for the 1/10 rule is the phase shift from the so-called "divider delay" (which is probably more accurately labeled "sampling delay"). Because the PFD only samples once every reference clock there is an equivalent average delay of 0.5/fref so in S-domain terms this can be expressed as exp (-0.5 * S / fref ). The phase shift of this sampling delay at fref / 10 is about 18 degrees. Any more phase shift than that and it gets pretty hard to stabilize the loop.

Title: Re: Why should CP - PLL have limited bandwidth?
Post by Hercules Poirot on Aug 8^th, 2017, 5:43am

Gardener derived the mathematics of it in his charge pump paper. There he derived the limit as 1/7.5 . Pavan Kumar Hanumolu did something similiar in 2007 (I think) where he showed the limit as approximately 1/4.
The intuition behind this goes something like this.
When you have a phase offset (let's say t1), the loop filter changes by (Icp/C2)*t1 during the time one of the current sources in the CP is turned on. Once both the current sources are turned off, the voltage across the C2 starts changing once again [now it depends upon the values of R, C1 and C2].
And all of this happened because you had a phase offset of t1 to begin with. So what is the net phase change? It is the integration of the control voltage waveform multiplied by the gain of the VCO.
If you run some simulations, you will find that higher bandwidth there is over correction. You don't want that. You limit the bandwidth so that there is only small correction of the entire phase error over the entire reference cycle.
You can also think of it as some linearity error. This process is not exactly linear. What Gardener proved was that the linearity holds (approximately) when the BW is less than the reference frequency by some factor.