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Design Languages >> Verilog-AMS >> Finite output impedance for a pure verilog coded output-reg node
https://designers-guide.org/forum/YaBB.pl?num=1483516765

Message started by subtr on Jan 3^rd, 2017, 11:59pm

Title: Finite output impedance for a pure verilog coded output-reg node
Post by subtr on Jan 3^rd, 2017, 11:59pm

Hi,

I have found that for the below code, the output is exponential based on the capacitance at the output node which suggests that the output is not an ideal voltage source against what I expected it to be.
Is this expected?
If it is compulsory that a digital out can only connect to another digital in, when I replacing the load block with a real block it would create a discrepancy because of this non ideal source behavior. In my test bench, I have a clock driving this block. I have also attached the waveforms.

`include "constants.vams"
`include "disciplines.vams"
`timescale 1ns/1fs

module veri_inv_test (dco_out, inv_in);

input inv_in;
output dco_out;
reg dco_out;

real nom_delay;

initial begin
dco_out = 1'b0;
nom_delay = 1/1e9;
end

always @(inv_in) begin
dco_out <= #nom_delay ~inv_in;
end

endmodule

Title: Re: Finite output impedance for a pure verilog coded output-reg node
Post by Andrew Beckett on Jan 4^th, 2017, 3:02am

You didn't really show what you have in the circuit to which the output of this Verilog is connected, but assuming it's just to an ideal capacitor, then what you're probably seeing is the RC caused by the output impedance of the L2E connectmodule (or whichever connect module you're using).

Most of the built-in connect modules have a default output impedance of 200 ohms, which would give a time constant of about 0.2ns with a 1pF cap - so that looks roughly right from the curves you've plotted.

You can reduce that - mostly you want a non-ideal connect module to better represent how the actual driver would behave when connecting to an analog circuit - in real life it wouldn't have zero output impedance.

Regards,

Andrew.

Title: Re: Finite output impedance for a pure verilog coded output-reg node
Post by subtr on Jan 4^th, 2017, 11:31am

Hi Andrew,

Thank you very much. I searched and found the path :

$AMSHOME/tools/affirma_ams/etc/connect_lib/connectLib/L2E/module/

and went through the code. :)