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Design >> Analog Design >> current mirror
https://designers-guide.org/forum/YaBB.pl?num=1483507944

Message started by joy on Jan 3^rd, 2017, 9:32pm

Title: current mirror
Post by joy on Jan 3^rd, 2017, 9:32pm

Hello,
will the operation of current mirror differ in sub-threshold region?
Thank you in advance.

Title: Re: current mirror
Post by vroy_92 on Jan 4^th, 2017, 11:38pm

Title: Re: current mirror
Post by nobody on Jan 9^th, 2017, 11:04pm

If you sim the current mirror and see how the sigma varies with W/L, I have some interesting observations.

Let's bias the mosfet with 1uA.
1. W/L has Vgst=200mV and 1 sigma is 10nA.
2. 2W/(0.5L) has Vgst=80mV and 1 sigma is 15nA.
3. 0.5W/2L has Vgst=500mV and 1 sigma is 5nA.
4. 2W/L has Vgst=140mV and 1 sigma is 8nA.
5. 16W/L has Vgst=-15mV and 1 sigma is 3nA.

From point 1 to point 3, the standard variation is improved while keeping W*L. This is expected.
However, from point 4 to 5, the sigma is improved even the mosfet is under subthreshold region.

I do not know the reason.
Could someone help?

Thanks

Title: Re: current mirror
Post by subtr on Jan 10^th, 2017, 1:01pm

I guess what you mean by 1 sigma is the random variation due to current mirror mismatch. Now let's think what would lead to more mismatch? If I had a very high gm, an difference in Vth between the mirror transistors will result in high current mismatch.

So the aim is "KILL THE GM"

Maintaining high W and L is a way to achieve lower mismatches in general. But pertaining to current mirror, increasing the L will improve the mismatch numbers and reduce random variations. If you assume square law, it is possible to prove that the mismatch only depends on L for a current mirror and it's inversely. But increasing the overall size is obviously going to reduce the Vt mismatch and effectively your current mismatch. For a given Vt mismatch, you will always find increasing length is the better option. Above all, Vt itself is a function of length. So all this is to be not taken for granted, because it might be that your Vt is very large that is helping you from mismatch for a particular length.

Title: Re: current mirror
Post by nobody on Jan 10^th, 2017, 9:54pm

I guess what you mean by 1 sigma is the random variation due to current mirror mismatch. Now let's think what would lead to more mismatch? If I had a very high gm, an difference in Vth between the mirror transistors will result in high current mismatch.

So the aim is "KILL THE GM"

Above stands from point 1 to point 3.

Maintaining high W and L is a way to achieve lower mismatches in general. But pertaining to current mirror, increasing the L will improve the mismatch numbers and reduce random variations. If you assume square law, it is possible to prove that the mismatch only depends on L for a current mirror and it's inversely. But increasing the overall size is obviously going to reduce the Vt mismatch and effectively your current mismatch. For a given Vt mismatch, you will always find increasing length is the better option. Above all, Vt itself is a function of length. So all this is to be not taken for granted, because it might be that your Vt is very large that is helping you from mismatch for a particular length.
I know that increasing L will improve Vt mismatch. But from point 4 and 5, I only increase width and the mosfet is in subthreshold region with 16W. In this subthreshold region, the mismatch is improved. This is what i do not get it

Title: Re: current mirror
Post by subtr on Jan 11^th, 2017, 9:43pm

I don't think there is any total escape from effect of width on the mismatch. Only for perfect square law device does the independence from width hold. Moreover, as you increase the size of the device, your Vt mismatch comes down as well. There are two components for the current one is gm and one is Delta_Vgs. If you increase width, gm increases. But the case you are looking at could be that Delta_Vgs is coming down due to reduction in mismatch. We should not assume that it's a monotonic function. It's a non linear function and there can be some local minima and maxima.

Title: Re: current mirror
Post by vroy_92 on Jan 13^th, 2017, 4:42am

I have my reservations about biasing current mirrors in sub-threshold region. The reason is that I do not trust the sub-threshold models very well, Vth mismatch if not modelled really well can be disastrous as the gm is higher for devices in sub-threshold region.