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Modeling >> Semiconductor Devices >> Igfinfet (independent gate finfet)
https://designers-guide.org/forum/YaBB.pl?num=1479472200

Message started by Bakr on Nov 18^th, 2016, 4:30am

Title: Igfinfet (independent gate finfet)
Post by Bakr on Nov 18^th, 2016, 4:30am

Hi,
I'm a new cadence user and I urgenly need to simulate igfinfet model shown here :
http://ece.ut.ac.ir/dsdlab/IG_FinFET.html
Can anyone rescue me with a tutorial or any data to simulat it.
Thanks in advance.
Regards;
Bakr

Title: Re: Igfinfet (independent gate finfet)
Post by Geoffrey_Coram on Nov 21^st, 2016, 5:06am

Ugh, that's a horribly-written model. The Verilog-A code (convertor.va) is a disaster.

It uses a signal-flow discipline
voltage G1,G2,G, temp;

instead of the conservative electrical.

And the actual equations are a mess:
analog V(temp) <+ (p00 + p10*V(G1) + p01*V(G2) + p20*pow(V(G1),2) + p11*V(G1)*V(G2) + p02*pow(V(G2),2) + p30*pow(V(G1),3) + p21*pow(V(G1),2)*V(G2)+ p12*V(G1)*pow(V(G2),2) + p03*pow(V(G2),3) + p40*pow(V(G1),4) + p31*pow(V(G1),3)*V(G2) + p22*pow(V(G1),2)*pow(V(G2),2)+ p13*V(G1)*pow(V(G2),3) + p04*pow(V(G2),4) + p50*pow(V(G1),5) + p41*pow(V(G1),4)*V(G2) + p32*pow(V(G1),3)*pow(V(G2),2)+ p23*pow(V(G1),2)*pow(V(G2),3) + p14*V(G1)*pow(V(G2),4) + p05*pow(V(G2),5));
analog V(G) <+ (V(temp)> 1.2)?(1.1):((V(temp) < -0.3)?(-0.2):(V(temp)));

If I'm reading that last line correctly, the expression for the gate voltage is discontinuous: it follows V(temp) between -0.3 and 1.2, but for V(temp) above 1.2, V(G) drops by 0.1 to 1.1 and then stays there, and has a similar discontinuity at -0.3

Stay away!