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Design Languages >> Verilog-AMS >> current measurement through $cds_iprobe
https://designers-guide.org/forum/YaBB.pl?num=1464253793

Message started by AMS_ei on May 26^th, 2016, 2:09am

Title: current measurement through $cds_iprobe
Post by AMS_ei on May 26^th, 2016, 2:09am

Hi, I am trying to measure current flowing through R2 with the help of verilog-AMS.

1. The following is my SPICE netlist file (input.scs):
//*************************************//
simulator lang=spectre
global 0
subckt TEST in out
R2 (in out) resistor r=1K
R1 (out 0) resistor r=1K
R0 (in 0) resistor r=1K
ends TEST

//*******************************************//

2. The following is my top.v file:

//******************************************//
module tb_top();
wire in;
wire out;

TEST test (
.in(in),
.out(out)
);

dc_gen Idc_gen(
.out(in)
);

curr_bfm Icurr_bfm (
.check_curr1()
);
endmodule

//***********************************************//

3. Following is the dc input voltage generator file which is basically the input voltage to the circuit

//********************************************
`include "disciplines.vams"
`include "constants.vams"
//`timescale 1ns/1ps

module dc_gen(out);
output out;
electrical out;

analog begin
V(out) <+ 5 ;
end
endmodule

//*********************************************//

4. Following is my amscf.scs file;

//************************************************//

***********

include "$TB_ROOT/test/input.scs"
include "$TB_ROOT/test/acf.scs"

amsd {
portmap subckt=TEST
config cell=TEST use=spice
}

//*******************************************//

5. Following the file with which I am trying to measure current through R2.

//***********************************************//
module curr_bfm(check_curr1);
output check_curr1;
electrical check_curr1;
real real_cur;
analog begin
real_cur = $cds_iprobe("tb_top.test.out");
I(check_curr1) <+ real_cur;
end
endmodule

//******************************************************//

6. Following is the probe.tcl file by which I am probing the signals.

//******************************************************//
probe -create -shm -all -analog -flow
run

//*******************************************************//

The above setting I am running with irun. But, there is no value of current showing through R2.

Could you please tell me if there is anything missing to get the value of current?

Thank you.

Title: Re: current measurement through $cds_iprobe
Post by Ken Kundert on May 28^th, 2016, 11:15am

Well, in your testbench you did not actually pass anything into your current checker:

Code:

curr_bfm Icurr_bfm (
.check_curr1() <---- this cannot be right
);

Second, you should never use $cds_iprobe unless you know what you are doing. It is inaccurate and when used in a circuit like this causes instabilities. Specifically, if you use $cds_iprobe you must first understand that it is inaccurate and how it is inaccurate so you know whether you can tolerate that inaccuracy. Second, you should never use the output of $cds_iprobe to drive the circuit itself.

Code:

module curr_bfm(check_curr1);
output check_curr1;
electrical check_curr1;
real real_cur;
analog begin
real_cur = $cds_iprobe("tb_top.test.out");
I(check_curr1) <+ real_cur;
end
endmodule

Instead, you should just use the normal mechanism for measuring current in Verilog-A.

Code:

module curr_bfm(check_curr1);
electrical check_curr1;
real real_cur;
analog begin
real_cur = I(check_curr1);
end
endmodule

Finally, this collection of models seems overly complicated and hopelessly confused. Perhaps if you described what you wanted to do we could just tell you how to do it. Regardless, you should read Introduction to Verilog-A.

-Ken

Title: Re: current measurement through $cds_iprobe
Post by AMS_ei on Mar 19^th, 2017, 10:03am

Hi Ken,

Thank you for your valuable inputs.
Actually, I would like to measure current of a SPICE net ( here in this context it is through out) with the help of Verilog-A/MS code.

Thank you.

Kind regards.

Title: Re: current measurement through $cds_iprobe
Post by Geoffrey_Coram on Mar 20^th, 2017, 1:04pm

What do you want to do with the current measurement? Do you want to print a message giving its value, or do you want to output a voltage (like a CCVS)?

Also, one can measure the current through a branch. If your "SPICE net" has more than two terminals, it doesn't really make sense to talk about measuring the current of the net.

Title: Re: current measurement through $cds_iprobe
Post by AMS_ei on Apr 18^th, 2017, 8:44am

Thank you Ken and Geoffrey Coram.
I got it now.