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Design >> Analog Design >> Theory to design a pierce oscillator (tough question)
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Message started by Pictou on May 21st, 2013, 2:19am

Title: Theory to design a pierce oscillator (tough question)
Post by Pictou on May 21st, 2013, 2:19am

Hello,
I'm trying to design a crystal oscillator (Pierce schematic). On the simulator (cadence) it works fine. However I would like to validate the simulation with some theory but I can't. My oscillator is oscillating (on simulation) at 40.1 Mhz, and I can't find why.

I'm just interested in knowing if the steps I took to calculate this oscillation frequency is correct or not. In the link below you will find a PDF showing my methodology. I decided to write it in a pdf because otherwise it would not be readable.

http://www.pdfhost.net/index.php?Action=Download&File=ea91ab67d9637ad314ac1238e8d78add

If someone could check my pdf and tell me if I made a mistake somewhere I would really appreciate.

2 options, either my calculations are wrong in theory, or my simulator is wrong....

Thank you very much for your help.

Title: Re: Theory to design a pierce oscillator (tough question)
Post by ywguo on May 23rd, 2013, 2:09am

HI Pictou,

First, you must know something about crystal model. What is the parameter of your crystal model? and its Q value?


Best Regards,
Yawei

Title: Re: Theory to design a pierce oscillator (tough question)
Post by Pictou on May 23rd, 2013, 3:19am

Hello ywguo,
Yes I asked the manufacturer he gave me the R1, L1, C1, C0. From this, Q is approximately 100 000.

Thank you.

Title: Re: Theory to design a pierce oscillator (tough question)
Post by ywguo on May 24th, 2013, 1:07am

Hi Pictou,

The Q value is good. What's the series resonant frequency with your parameter?

fs=1/(2*PI*sqrt(L1*C1))

Best Regards,
Yawei

Title: Re: Theory to design a pierce oscillator (tough question)
Post by Pictou on May 24th, 2013, 1:25am

fs = 40.026 MHz.

Thing is, I can't find this result back from the analysis of the schematic.

I mean, wherever I read something about oscillators, it says that it's really hard to start oscillation; that C1 and C2 (for load capacitance) must be chosen carefully.
BUT I can't chose them wisely if I don't even know how my schematic works (theoretically at least).

What I would like to do is find this expression of fs by analyzing my schematic. Also, I would like to be able to calculate the voltage across the oscillator, the current through it, etc etc...


I think my mistake is that I assumed that X1 + X2 + X3 = 0, it can't be 0 as the crystal is not a perfect inductor... still investigating though.

Title: Re: Theory to design a pierce oscillator (tough question)
Post by ywguo on May 24th, 2013, 5:11pm

Hi Pictou,

I think that X1+X2+X3=0 is eventually correct if the oscillator starts up. However, it seems that you have not read some literatures about crystal oscillator design. This is a link that I googled just now.  :)
http://electronicdesign.com/analog/fundamentals-crystal-oscillator-design


Quote:
I mean, wherever I read something about oscillators, it says that it's really hard to start oscillation; that C1 and C2 (for load capacitance) must be chosen carefully.

Yes, the designer must choose C1 and C2 carefully, but usually not very very carefully. The available values of C1 and C2 vary in a very big range. It says that it's really hard to start oscillation just because the authors have to say something to emphasize the importance of their analysis and circuit design skills.  :)

I think the most important paper on crystal oscillator deisgn is High-performance crystal oscillator circuits: theory and application by Eric Vittoz, etc, in JSSC 1998.

Best Regards,
Yawei

Title: Re: Theory to design a pierce oscillator (tough question)
Post by Pictou on May 27th, 2013, 6:50am

Okay I'll read this article, I'm sure it will help.

Thank you very much.
EDIT : I've been trying to design an oscillator for 3 months now... I haven't found anything relevant in most of the things I read. And you managed to find a reliable source of information with just one google search... I've been on google for a while... must have typed something wrong.

Title: Re: Theory to design a pierce oscillator (tough question)
Post by raja.cedt on May 28th, 2013, 12:14am

Hello,
You could think of think of this problem like a Colpitts oscillator as well. Calculate how much inductance your crystal has at it's series or // resonance frequency.

Normally C1/C2 start-up requirement as well noise(i suppose this is less critical for you). Initial guess would be C1/C2 is around 1, which gives easy start up (around 4 loop gain you need).

Thanks,
Raj.

Title: Re: Theory to design a pierce oscillator (tough question)
Post by Pictou on Jun 10th, 2013, 1:55am

Hello, well after a few days trying to fit the theory to my simulation... it doesn't work one bit, I'm sure I'm doing something wrong and I don't know what.

Anyway, I'm getting short on "free" time and need to work on something else.

The article and the colpitts approach allowed me to understand a little better. I'm also sure that the results they get are correct, so it must be my numerical application that doesn't fit.

Thank you all for your help!

Title: Re: Theory to design a pierce oscillator (tough question)
Post by Kevin Aylward on Jul 6th, 2013, 3:11am

First, what you posted is the generalised Colpitts oscillator. That is, ANY single device configuration that has a capacitor, effectively across its drain source and a capacitor across its gate source. A Pierce is defined as having a resister from the drain in series with the drain capacitor, to form a pi network. This resister is important. It reduces both sensitivity to DC supply, and lowers 1/f up converted phase noise. Always use it, period, unless you simply don’t have enough gain at frequency.

Ignore all the equations. There are useless. All xtals in the known 3 universes from manufactures are specified to run on only a handful of standard load capacitances. These will be, 30p/2, 20p/2 or 13.5pf/2. i.e.  make the caps the same. To check enough loop gain stick a voltage source in the gate lead and run Cadence stb analysis. Run transients with a “DeQed” xtal of say, 100 times. i.e. multiply the c1, series capacitor by 100. C1 is typically 1ff to 20ff. Use 10ff X 100 as a starter. The bigger the cap, the more frequency stable but harder to get the gain at high frequencies.


Title: Re: Theory to design a pierce oscillator (tough question)
Post by Pictou on Jul 8th, 2013, 12:27am

Thank you for your help. I abandoned the equations, they don't seem to work and there is no "real application on a real case" to be found... even on the internet.

About the resistor in series, do you mean like the figure 2 page 3 of this link?

http://www.freescale.com/files/microcontrollers/doc/app_note/AN3208.pdf

It says that I only need it in case I have too much drive level, however nobody knows how to define this resistor as there is no equation to prove anything. So I just tossed it and it works fine as I managed to get oscillations without consuming much.


To calculate power, I used the mean value of V * I going through the C1 capacitor (as it gave me the biggest power). Thing is, I don't know why in every books and on the internet they use P = R * I² as V and I are not even in phase...

Title: Re: Theory to design a pierce oscillator (tough question)
Post by Kevin Aylward on Jul 8th, 2013, 10:25am

Yes, that’s the resistor. As I noted, the “Pierce resistor” was invented as a design technique to get better frequency stability. It is not necessary, but if cost and space are not an issue, it is better to use it. Yes, it can also be used to control drive current, but that was not why the topology was invented. A starter value is 1k. Depends on frequency. Too large and it will stop oscillating. To get xtal power, it’s the power in the esr resistor of the xtal. That is, the model has a L C1 ESR in series and a parallel Co. The voltage and current are always in phase in a resistor, irrespective of what else it may be attached to. In checking oscillation in simulation, use a value of esr up to 3 times the rated esr. This is because start up esr can be higher than running esr. Do not use the esr as a way of lowering Q for transient runs. Q lowering is always done by way of changing c1. Most spices will allow a equations with parameter to do this easily.

Title: Re: Theory to design a pierce oscillator (tough question)
Post by Pictou on Jul 9th, 2013, 12:30am

Thank you very much for your help, I understand now better why some schematic includes the resistor and some doesn't.

About the resistor power, I still have a problem.  If I can do P = R*I² I can also do : P = U²/R. So I decided to plot the U across the R.

Please find below V1 and V2 (Voltage level across the resistance) and then V1 - V2 AND the current.

http://www.hostingpics.net/viewer.php?id=640763voltageacrossESR.png


http://www.hostingpics.net/viewer.php?id=723730voltagedropandcurrent.png


As you can see on the first image, even the voltage is not in phase after crossing the resistor.

In the second screenshot, I made V1-V2 and plotted the current crossing the R resistance and it's not in phase either. So, I'm kind of lost... My guess is, it's not in phase because L and C are in series with R. Maybe I'm wrong, could you help me again please? Thank you again.

Title: Re: Theory to design a pierce oscillator (tough question)
Post by Kevin Aylward on Jul 9th, 2013, 10:57am

The voltagedropandcurrent.png show the current and voltage perfectly in phase!

Title: Re: Theory to design a pierce oscillator (tough question)
Post by Pictou on Jul 10th, 2013, 12:26am

Actually they are not, I just made the trace thick so it wouldn't be too ugly with my screenshot. I should have let it as "fine trace".

If you look at the 0 level for instance, you can see that the green curve is too much on the right (or the red one is too much on the left).

All I'm saying is, I would like to use P = R*I², but for now, I can't justify why it would be correct. Even the first trace doesn't make sense to me, the two voltages are not in phase...

In all books I read and on the internet, almost everyone is using P = R*I² but they don't justify why. There is a phase to consider in all these signals but they don't seem to care.

Title: Re: Theory to design a pierce oscillator (tough question)
Post by Kevin Aylward on Jul 10th, 2013, 9:30am

The laws of physics demand that the voltage across a resister is in phase with its current. Possibly simulator needs to be set with tighter tolerances, and more time points, or Ken has built in a deliberate error in Spectre to annoy people. The rest of the xtal is all lossless components, hence cannot dissipate any heating power. All power in the XTAL black box must therefore be due to the resistor.  

Title: Re: Theory to design a pierce oscillator (tough question)
Post by Pictou on Jul 11th, 2013, 5:14am

Thank you for your help, it does make sense!

PS : your tutorial on startup circuit is really well written, thank you for sharing this.

Title: Re: Theory to design a pierce oscillator (tough question)
Post by loose-electron on Aug 2nd, 2013, 7:31pm

Couple things on simulating with a high Q crystal -

The high Q will lead to errors in resolution due to the extreme narrowness of the resonance.
(you actually miss the peak of the curve in the frquency steps, unless you get really small and thus slow simulations)

This also leads to really slow start times for transient simulations.

Tricks:

Drop the Q down a lot in the crystal model, this will speed simulation and you won't need micro steps when frequency sweeping. This will also speed you start-up time as oscillation builds.

Other useful item - instant start of the simulation instead of waiting for it to slowly build up - put an initial condition of current on the inductor in the crystal model. This will give you an instant start for the crystal.

THis has been discussed here before.


Title: Re: Theory to design a pierce oscillator (tough question)
Post by Kevin Aylward on Aug 3rd, 2013, 1:28am

It would be a good idea to set up a parameterised model of the xtal. A generic model would be like:

.SUBCKT XTAL 1 2 c1=1p esr=50 f=10M c0=2p
Cp 1 2 {c0}
Ls 1 3 {0.025330295/f/f/c1}
Cs 3 4 {c1}
Rs 4 2 {esr}
.ends

In Cadence you can use the CDF to set a parameterised symbol for a schematic block. The inductor inductance field can contain the equation. The Q can then be varied as desired by changing c1. Typical c1’s will be from  1ff to 20ff for full Q, and 1pf for sims that finish this week.

Title: Re: Theory to design a pierce oscillator (tough question)
Post by ricardo80 on Nov 1st, 2013, 10:03am

@Pictou: I think your simulation is ok if it works well and there is problem in the calculation of the frequency and if it does not work well try to adjust the values of R,L and C because the frequency of oscillation of the oscillator depends upon the these parameters.

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