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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> verilog-a question https://designers-guide.org/forum/YaBB.pl?num=1256646704 Message started by filipe on Oct 27th, 2009, 5:31am |
Title: verilog-a question Post by filipe on Oct 27th, 2009, 5:31am How to access voltage and current signals that are at other blocks in my system, using veriloga language (not verilogams)???? With which code can I do this? Thanks in regards. Filipe |
Title: Re: verilog-a question Post by rajdeep on Oct 27th, 2009, 9:13am To access voltage at a given node (say n) and/or current thru an electrical branch (say p,q) you have to use the access functions like V(n) and I(p,q) respectively. You can save these values in a real variable by writing vol = V(n); curr = I(p,q). Note that to probe a voltage between two nodes say A and B you have to write vol = V(A,B). If you are not very new to Verilog-A then what I said above must be known to you!! Now, what do you mean by signals in other blocks in your system??? Do you want to probe signals which are in other design blocks (may be in other hierarchy also) in a different block, which you are implementing using Verilog-A? Sounds like monitoring something...and I will assume that. The easiest way is to bring all those signals to the interface of your monitor block as pins. But then accessing current is not possible in that way, unless you place the monitor block between the two nodes p and q, Finally, to probe current using I(p,q) approach make sure p and q are shorted in your design!! Let me know if what said made any sense? :-? Rajdeep |
Title: Re: verilog-a question Post by filipe on Oct 27th, 2009, 9:46am Hello rajdeep, Thanks for your answer. Yes, that is the question. I would like to use only veriloga to monitor voltages and currents in other hierarchy, and I dont like to use verilogams. Regards Filipe |
Title: Re: verilog-a question Post by rajdeep on Oct 27th, 2009, 11:57am Ok! Thats fine. May I know which tool you are using for designing? If it is Cadence ICFB (DFII) I can provide you some help I guess, as I once tried doing such things and was able to do it. Having said that, I had to insert current probes in all those required branches. cheers! Rajdeep |
Title: Re: verilog-a question Post by somisetty on Nov 9th, 2009, 5:10am Hi, i am new to verilogA, Already rised this question but the problem is that i am using to simulate through Spectre simulator(Cadence) and also VerilogA. I had a sub blocks like NOT and NAND which are connected shown in below with VerilogA code(Its an behavioural). The rise/fall time for inverter has given using CDF parameter then i get the output of inverter with some delay and the same output of inv has to be connected to input of NAND gate(that means the slew rise/fall of inv is to be the input slew rise/fall of one input of NAND gate). How i have to interdepended to each other using CDF parameters of NAND gate? One more, does can make CDF parameter as global parameter? Please provide me answer as soon as possible... Thank inadvance, |
Title: Re: verilog-a question Post by Geoffrey_Coram on Nov 9th, 2009, 10:23am I don't fully understand your approach, but it seems that, if you're trying to model loading, you should write a more sophisticated behavioral model, such that it effectively outputs a current that is integrated on the input capacitance of the next stage. Then, the more gates in the next stage, the slower the rise. |
Title: Re: verilog-a question Post by Peng_Li on Dec 2nd, 2017, 11:44pm Hi, I also run into this problem recently. I want to calculate the power consumed by an inverter in Verilog-A. But simultaneously accessing voltage and current result in error report in Hspice simulation. To make it simple, I will use a resistor to describe my problem. First, I defined two modules in verilog-a, a resistor and a voltage source, with the examples provided by this website. Second, I instantiate these two modules in another module A, and try to access both the voltage and current across the resistor. However, this would result in error report when simulated in Hspice, as following. hsp-vacomp: Error: Accessing both the flow and potential of a probe branch hsp-vacomp: ( Unnamed branch (input1, ngnd), module 'test_pwr_of_res' ) is prohibited. This error report disappear when I define the branch (input1,ngnd). However, it then output nothing but zero on the node getpwr The resistor module is as following. Code:
The voltage source module is as following. Code:
The top-level module is as following. Code:
Does anyone come across this kind of problem? Any help would be greatly appreciated. |
Title: Re: verilog-a question Post by Geoffrey_Coram on Dec 4th, 2017, 5:12am You really should have started a new thread, since the original thread was 8 years old, did not have a helpful title ("verilog-a question"), and wasn't really related to the question you are asking. If I answer it here, I'm not sure anyone else will ever see it. |
Title: Re: verilog-a question Post by Geoffrey_Coram on Dec 4th, 2017, 5:24am I usually work on device models, where the currents are computed as a function of the input voltages. Eg, showing just the key lines of a simple diode model: Code:
In that case, one can easily compute the power by simply multiplying the variables vd * id. In your case, if you want to compute the power from outside the resistor, you need to add a current probe Code:
Per the VAMS LRM, section 5.4.2.1 Probes: If no value is specified for either the potential or the flow, the branch is a probe. If the flow of the branch appears in an expression anywhere in the module, the branch is a flow probe, otherwise the branch is a potential probe. Using both the potential and the flow of a probe branch is illegal. The branch potential of a flow probe is zero (0). The branch flow of a potential probe is zero (0). 5.4.2.2 Sources For the branch (input1,input1a), no value is specified for the potential or the flow, so it is a probe; since the flow of the branch I(input1,input1a) appears in an expression, it is a flow branch and its potential is zero. Effectively, I'm adding a 0V voltage source to measure the current. |
Title: Re: verilog-a question Post by Peng_Li on Dec 8th, 2017, 8:06pm Thanks a lot for your help, Mr. Coram. The first method you mentioned works well, namely, calculating the circuit's total power by multiplying the voltage and current in the analog block of the excitation source module (whether it is voltage or current source). The second method is really subtle and delicate. I mean, the skillful I(input1,input1a). It works well both for resistor load or capacitor load even without explicitly define the branch. However, when I applied the second method to the 6 order inverter case, shown as following, Hspice refuses to work and doesn't give any message. I have two questions. (1)I wonder whether it is because the inverter is implemented by calling a subcircuit of inverter in Hspice, which cause some confusion for the simulator. (2)If so, I tried to implement the inverter in Verilog-a. From your discussion in a former thread (http://www.designers-guide.org/Forum/YaBB.pl?num=1274466479), I found your paper on the 2014 conference and BSIM4v5. To avoid my self-written probably bad code, I want to use the BSIM4v5 directly in Verilog-a module. But the BSIM4v5 are written in C. So is it possible to call it in Verilog-a and conduct simulation in Hspice? Thanks in advance. The module to calculate the power of inverter is as following. Code:
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Title: Re: verilog-a question Post by Geoffrey_Coram on Dec 11th, 2017, 12:02pm Quote:
That's unusual. You might try sending the test case to Synopsys. I have only limited experience trying to put Spice instances in a Verilog netlist; I usually put Verilog-A instances in my Spice netlist. There's a section (appendix) of the Verilog-AMS LRM that talks about Spice compatibility, but you may need to review the HSpice manual for vendor-specific details. Or you could pull the three terminals (input1, input1a, ngnd) out as terminals and hook them up to the Spice subckt to get the measurements, leaving the inverter in Spice. |
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