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Design Languages >> Verilog-AMS >> how to model a gated voltage controlled oscillator
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Message started by beabroad1 on Jun 24^th, 2005, 4:27pm

Title: how to model a gated voltage controlled oscillator
Post by beabroad1 on Jun 24^th, 2005, 4:27pm

i want to model a gated voltage controlled oscillator.
that is to say, there is two inputs, one is Vgate and the other is Vfreq.
when Vgate is ONE, the VCO stops.
when Vgate is ZERO, the VCO start to oscillate, and its initial phase is zero.
i am a new comer to the verilog AMS language, and use Cadence IC design platform to run the simulation.
thank you for your help.