The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> How to implement the INL&DNL of ADC in verilog
https://designers-guide.org/forum/YaBB.pl?num=1103513240

Message started by tanjp on Dec 19^th, 2004, 7:27pm

Title: How to implement the INL&DNL of ADC in verilog
Post by tanjp on Dec 19^th, 2004, 7:27pm

???,how to implement the INL&DNL of ADC in verilog-A/AMS? And why are the input resistor and the input capacitance used in the ADC?What is the function?

Title: Re: How to implement the INL&DNL of ADC in ver
Post by sheldon on Dec 19^th, 2004, 8:35pm

Hi,

If you have access to ADE, look at the adc_8bit model,
DNL is implemented in the model. One cavaet, you may
need to add re-normailization so the output range with
DNL is correct. INL is easier, it just requires implementing a
non-linear transfer function from input to output.
For example,
V( mid) = V( in) * gain + HD2 * V( in)^2 + HD3 * V( in)^3 ...
where V(mid) is the actual voltage that is used for the
conversion. Depending on whether or not your ADC
model is differential out, you can drop the HD2 term.

Sheldon

Title: Re: How to implement the INL&DNL of ADC in ver
Post by andraw on Jan 16^th, 2005, 12:26am

O year, I wan to know also.[glb][/glb]

Title: Re: How to implement the INL&DNL of ADC in ver
Post by sheldon on Jan 23^rd, 2005, 4:52pm

Greetings,

Forgot to mention, the input resistor and capacitor are
either:
1) The input load of the ADC, driving an ADC is a very
difficult issue. In real ADCs, the capacitance is often
large and non-linear. Driving ADC are a key application
for very high performance op-amps because of the ADC
input load.
2) The input resistor and capacitor maybe used to model
the analog bandwidth of the ADC. The 3dB bandwidth
of the input limits the maximum input frequency.