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Design Languages >> Verilog-AMS >> Array size function in Verilog-A/AMS?
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Message started by mmirmak on Dec 3^rd, 2004, 11:04pm

Title: Array size function in Verilog-A/AMS?
Post by mmirmak on Dec 3^rd, 2004, 11:04pm

I have a simple question regarding determining the size of arrays in Verilog-A and Verilog-AMS.

If I have a function which will accept, for example, an array of reals, how may I determine within the function the size of the array? In other words, do I have to pass the array size into my function as an explicit integer variable? Is there some "sizeof" function in Verilog-A or Verilog-AMS which would allow me to determine the size of the array a priori?

Thanks!

Title: Re: Array size function in Verilog-A/AMS?
Post by Geoffrey_Coram on Jun 6^th, 2005, 8:53am

I'm not aware of a way to determine the array size.

Since in Verilog (1364), arrays have to be declared using constant_expressions for the address ranges, it seems that one wouldn't need to query the array (it can't grow during the simulation), other than to avoid passing an additional argument.