Hi,

This is my first post, so I hope it's not a bad question or anything.

I'm trying to learn Verilog, and I wanted to ask if the following 2 are identical in making a 4 bit counter.

Thank you!
Jason


*********** #1 ***********

module counter(clk, rst, ld, q3, q2, q1, q0);
   input clk;
   input rst;
   input ld;
   output q3;
   output q2;
   output q1;
   output q0;

always @ (posedge clk)
begin
     if (rst == 1'b1)
           [q3,q2,q1,q0] = 4'd0;
     else if (ld == 1'b1)
           [q3,q2,q1,q0] = 4'b1;
     else
           [q3,q2,q1,q0] = ([q3,q2,q1,q0] + 1) % 16;
end
endmodule

*********** #2 ***********

module counter(clk, rst, ld, q3, q2, q1, q0);
   input clk;
   input rst;
   input ld;
   output q3;
   output q2;
   output q1;
   output q0;
   wire [3:0] Q;
   reg [3:0] C;

   assign Q = {q3,q2,q1,q0};

   always@(posedge clk or posedge rst)  // reset
   begin
    if(rst) C <= {4'b0000};
     else
      C <= Q + 1;
     end

      assign q3 = C[3:3];
      assign q2 = C[2:2];
      assign q1 = C[1:1];
      assign q0 = C[0:0];
endmodule