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The Designer's Guide to Verilog-AMS
The Designer's Guide to SPICE and Spectre Contents
Preface
1. Introduction (excerpt)
2. Top-Down Design (excerpt)
3. Analog Modeling (excerpt)
4. Mixed-Signal Modeling (excerpt)
5. Language Reference (excerpt)
A. Compatibility (excerpt)
References
Index

The Designer's Guide to Verilog-AMS starts in Chapter 1 with a brief introduction to hardware description languages in general and Verilog-AMS in particular.

Chapter 2 presents a formal top-down design methodology. While not used extensively today, top-down design is widely believed to be the only methodology available that can efficiently handle large complex mixed-signal designs. This chapter presents a refined and proven top-down methodology that overcomes many of the problems with existing top-down methodologies.

Chapter 3 and Chapter 4 introduce the Verilog-A and Verilog-AMS languages. The important concepts of the languages are presented using practical and easy to understand examples. These chapters are intended to be read from beginning to end and are designed to take engineers with a working knowledge of programming concepts to the point where they are comfortable writing a wide range of Verilog-A and Verilog-AMS models. However, they do not cover all the details of the languages.

Chapter 5 is a reference guide to the languages. It presents all of the details, but not in a completely linear fashion. Though it can be read from beginning to end, it was written with the expectation that most would use it as a reference, looking up just the details they need when they need them. As such, it, as with the rest of the book, is extensively cross referenced and indexed.

Appendix A covers some of the practical details of using Verilog-A or Verilog-AMS with several available simulators.

The most recent versions of the examples used in the book are available for download below. All Verilog-A models have been tested with Spectre. All Verilog-AMS models have been tested with AMS Designer.

ISBN 1-4020-8044-1 (hardbound)
ISBN 1-4020-8045-X (eBook)
Library of Congress Call Number TK7874 .K856 2004
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Examples
The following are the most recent versions of the examples used in the book.
Chapter 3: Analog Modeling
Listing 1: linear resistor Listing 15: linear shunt RLC
Listing 2: linear conductor Listing 16: resistive port
Listing 3: linear capacitor Listing 17: ideal relay
Listing 4: linear inductor Listing 18: relay
Listing 5: constant-valued voltage source Listing 19: non-ideal relay
Listing 6: constant-valued current source Listing 20: ideal mechanical stop
Listing 7: simple structural model Listing 21: ideal diode
Listing 8: abbreviated version of example 7 Listing 22: sinusoidal voltage-controlled oscillator
Listing 9: motor and testbench Listing 23: ideal periodic sample and hold
Listing 10: electrical and rotational disciplines and natures Listing 24: periodic sample and hold
Listing 11: junction diode Listing 25: time interval measurement
Listing 12: simple diode with series resistance Listing 26: analog to digital converter
Listing 13: voltage-controlled voltage source Listing 27: digital to analog converter
Listing 14: linear series RLC Listings 28 & 29: lossy inductor with skin effect
Chapter 4: Mixed-Signal Modeling
Listing 1: inverter Listing 11: digitally controlled switch with resistance
Listing 2: logic discipline Listing 12: analog to digital converter
Listing 3: inverter Listing 13: voltage controlled oscillator
Listing 4: simple clock generator Listing 14: comparator
Listing 5: edge-triggered d flip flop Listing 15: mixed-signal netlist
Listing 6: two-input latch Listing 16: basic electrical-to-logic connect module
Listing 7: counter Listing 17: enhanced electrical-to-logic connect module
Listing 8: digital frequency measurement Listing 18: simple digital-to-analog connect module
Listing 9: digital to analog converter Listing 19: bidirectional connect module
Listing 10: digitally controlled switch Listing 20: bidirectional connect module with driver access
Chapter 5: Language Reference
Listing 1: ideal opamp Listing 4: warn on breakdown
Listing 2: pseudo-random bit stream generator Listing 5: comparator
Listing 3: d flip flop
Appendix A: Compatibility
Listing 1: N-level quantizer Listings 2-9: phase-locked loop
Listing 10: phase-locked loop with analog reference clock
Permission to make copies of these models for personal or classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage. To distribute otherwise, to publish, to post on servers, or to distribute to lists, requires prior written permission. Extract models from .tgz files using "tar -zxvf filename.tgz".
Errata
Errata to first edition (last updated on 1 October 2007)
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